Anritsu MT8820A - Power-on Procedure

2.2
2.22.2
2.2 Circuit Description of Each Unit
Circuit Description of Each UnitCircuit Description of Each Unit
Circuit Description of Each Unit
2-
2-2-
2-55
5555
55
Fig. 2-14 Block Diagram of A03 AUDIO Unit
PLX
9054
A/D
P
→
S
P
←
S
FIFO
DSP 1
Core A
DSP 1
Core B
FIFO
FIFO
DSP 2
Core A
DSP 2
Core B
FIFO
FIFO
S
←
P
ADDRESS
DECODE
FPGA1
A/D
FIFO
S
←
P
D/A
FIFO
S
→
P
D/A
FIFO
S
→
P
P
→
S
P
←
S
FPGA2
FPGA2
RAM