Anritsu SQA-R MP1900A - SI PPG;ED Link Training Features; PCI Express Link Training; USB Link Training Functionality

10
SI PPG/ED Link Training
The PCI Express and 10 Gbit/s USB3.2 standards require PHY layer tests
such as Jitter Tolerance tests on an established Link to assure
interconnectivity between the host and device. Additionally, it is
necessary to determine whether the cause is a physical or logical fault
at a Link fault.
The MP1900A PCI Express/USB functions have Protocol Awareness with
a Link Training function required for evaluating the PHY layer as well as
an analysis function for detecting each LTSSM state transition to help
troubleshoot faults. When more detailed debugging is required, the
training sequence generation timing can be adjusted using the
Sequence Editor function (MU195020A-050).
These all-in-one functions facilitate efficient PHY layer evaluation of
PCIe Gen1 to Gen5 and USB3.2 receivers through inspection and fault
troubleshooting.
Moreover, combination with the Jitter Tolerance Measurement function
(MX183000 A-PL001) supports consistent receiver tests of high-speed
serial interfaces.
LTSSM: Link Training Status State Machine
Supports physical layer measurements of add-in cards and system
boards
• Tx LEQ: Transmitter Link Equalization response Test
• Rx LEQ: Receiver Link Equalization Test
• Receiver Jitter Tolerance Test
MP1900A DUT
Transcation Transcation
Data Link Data Link
Physical Physical
Rx Tx TxRx
Logical Sub-block Logical Sub-block
Electrical Sub-block
Electrical Sub-block
ED PPG
Link Training
PCI Express Link Training (MX183000A-PL021/PL025)
PCIe Link Training State Transition
USB Link Training State Transition
LTSSM Log of each LTSSM State Transition
LTSSM Log of each LTSSM State Transition
USB Link Training (MX183000A-PL022)