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Application Examples
PCIe Gen3/4/5 CEM Specification Receiver Test
PCI Express CEM Solution Features
• All-in-one support for Protocol Awareness PCIe Gen1 to Gen5 receiver
tests
• Event Trigger Function for Tx/Rx Link Equalization Test
• 2.4 Gbit/s to 32.1 Gbit/s high-speed BERT
• Low-intrinsic-jitter and high-quality output waveform, high-sensitivity ED
• Link Training, Link Equalization and LTSSM analysis functions
• 10Tap Emphasis function
• 12 dB CTLE and Clock Recovery functions
• CMI and DMI Noise addition, and SJ, RJ, BUJ, and SSC Jitter Addition
functions
• Thunderbolt 3, USB3.2/4, PCI Express Gen5 support
• Full automation including CBB control
PCIe CBB Controller Z2025A
The DUT must be reset and transitioned to the Initial state before
starting Link Training.
The PCIe CBB Controller Z2025A fully automates control of Rx LEQ and
Tx LEQ using the Power Reset and Power Cycle control pins
implemented by PCIe CBB 4.0 (Compliance Base Board 4.0).
Matrix Scan Function
To secure high-quality communications with the Link partner, the best
combination of the Tx-side EQ and Rx-side EQ must be selected.
The Matrix scan function scans for the best Tx EQ setting at the receiver
to find the best setting automatically at the receiver.
Link Training Function (MX183000A-PL021/PL025)
The PCI Express receiver test requires establishment of the Link status
using LTSSM before performing the DUT BER test.
Installing the PCIe Link Training option in the MP1900A supports
verification of the Link status required for measurement. This option has an
LTSSM Analysis function for troubleshooting problems the Link status
cannot be configured.
Required Items
• Link Training function
• Jitter Tolerance Test
• Emphasis Eect Validation
• Supports Common/Separate Clock Architecture
DUT
AIC
CBB
CBB
Oscilloscope
100 MHz
Ref. Clock In
Tx out
Rx in
Synthesizer
Jitter Modulation Source
Noise Generation Source
PPG
ED
MP1900A
CBB Controller
Z2025A
Remote Control
Test Report
Test signal calibration
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