Anritsu SQA-R MP1900A - Page 25

25
Module Selection Guide
Category Model/Name
21G or 32.1G
1ch BERT
32G Interconnects,
Signal Integrity/
Measurement
USB3.2
Receiver Test
USB Type-C, DP
Receiver Test
100 GbE 4ch
Backplanes/AOC
Main Frame
Signal Quality Analyzer-R
MP1900A
1 1 1 1 2
Synthesizer
12.5 GHz 4 Port Synthesizer
MU181000B
1 1 1 1 1
Jitter Modulation Source
MU181000B-001
SSC Extension
MU181000B-002
Jitter
Modulation
Jitter Modulation Source
MU181500B
1 1 1 1
21G/32G PPG
21G/32G bit/s SI PPG
MU195020A
1 1 1 1 2
32G bit/s Extension
MU195020A-001
(1) 1 2
1ch Data Output
MU195020A-010
1 1 1 1
2ch Data Output
MU195020A-020
1*
9
2
1ch 10Tap Emphasis
MU195020A-011
1 1 1
2ch 10Tap Emphasis
MU195020A-021
1*
9
2
1ch Data Delay
MU195020A-030
2ch Data Delay
MU195020A-031
2
1ch Variable ISI
MU195020A-040
1
2ch Variable ISI
MU195020A-041
2
Sequence Editor Function
MU195020A-050
1*
10
21G/32G ED
21G/32G bit/s SI ED
MU195040A
1 1 1 2
32G bit/s Extension
MU195040A-001
(1) 1 2
1ch ED
MU195040A-010
1 1 1
2ch ED
MU195040A-020
2
1ch CTLE
MU195040A-011
1 1
2ch CTLE
MU195040A-021
2
Clock Recovery
MU195040A-022
1 1 2
Voltage Noise
Noise Generator
MU195050A
1 1*
8
1 2
White Noise
MU195050A-001
2
Software
Jitter Tolerance Test
MX183000A-PL001
1 1 1
PCIe Link Training
MX183000A-PL021
PCIe 5 Link Training
MX183000A-PL025
USB Link Training
MX183000A-PL022
1
*
8: Not required when using Pick Off Tee J1510A (2 pcs).
*
9: The DP receiver test requires 2 channels.
*
10: Used at USB3.2 Link Training debugging