Anritsu SQA-R MP1900A - Module: 12.5 GHz 4 port Synthesizer MU181000 B; Module: Jitter Modulation Source MU181500 B; Module: 28 G;32 G bit;s PPG MU183020 A; Module: 28 G;32 G bit;s High Sensitivity ED MU183040 B

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Signal Quality Analyzer-R MP1900A Panel Layout
Modules
12.5 GHz 4port Synthesizer MU181000B
Jitter Modulation Source MU181500B
1
 10MHzBuOutput
Output 10 MHz clock for reference
2
10 MHz Ref Input
Inputs 10 MHz clock for reference
3
100 MHz Ref Input*
1
Inputs 100 MHz clock for reference
4
Ext I, Q*
2
Inputs I, Q signals
1
IQ Output
Outputs IQ signal
2
Ext Jitter Input
Inputs Jitter Modulation Source
3
Sub-rate Clock Output
Dierential Clock Output signal generated from 1/8 to
1/256-divided Clock Output based on any of following Clock
inputs
• Ext Clock Input • Aux Input
4
Aux Input
Inputs clock signal
1 53 72 64
1 53 72 64
5
Trigger Output*
2
Outputs 1/1 or 1/64 clock frequency
6
Jitter Ext Input*
2
Inputs modulation signal source
7
Clock Output 1 to 4
Outputs clocks
*
1: Only when Jitter Modulation Option (MU181000B-001) or SSC
Extension (MU181000B-002) installed
*
2: Only when Jitter Modulation Option installed (MU181000B-001)
5
Reference Clock Output
Dual-system Clock Output signal generated from either 1/1,
1/2, or 1/4-divided Jitter Clock Output based on any of
following Clock inputs
• Ext Clock Input • Aux Input
6
Jittered Clock Output
Two outputs jitter modulated clock signal
7
Ext Clock Input
Inputs external clock
28G/32G bit/s PPG (1ch or 2ch) MU183020A
1
Data1/Data1 Output*
3
Output for 1ch dierential data signal
2
Data2/Data2 Output*
4
Output for 2ch dierential data signal
3
Gating Output
Output for burst timing signal
4
Aux Input
Input for auxiliary signal
5
Aux/Aux Output
Output for dierential auxiliary signal
6
Clock Output
Output for clock signal
7
Ext Clock Input
Input for external clock signal
*
3: Data/Data when 1ch option was selected.
*
4: Not implemented when 1ch option was selected.
28G/32G bit/s High Sensitivity ED (1ch or 2ch) MU183040B
1
Data1/Data1 Input*
5
Input for 1ch dierential data signal
2
Data2/Data2 Input*
6
Input for 2ch dierential data signal
3
Aux Input
Input for auxiliary signal
*
5: Data/Data when 1ch option was selected.
*
6: Not implemented when 1ch option was selected.
4
Aux/Aux Output
Output for dierential auxiliary signal
5
Ext Clock Input
Input for external clock signal
1 53
7
2 64
1
5
3
2
4