video outputs active, resolution & copy protection limits apply. Also, when
displaying 408i/576i the colour space requirements of the ADV7310 &
SiI9134s are incompatible, so if an HDMI display is connected the analogue
outputs are muted.
The PW338 can only output one clock pulse per pixel, so for 480i & 576i
resolutions, a video clock doubler is required (IC504 ICS2402MLF) to convert
the 13.5MHz pixel clock (Display Clk) to 27MHz (Display Clk2) under the
control of Vid_Clk_Sw.
The output of the ADV73120 is filtered by IC500 (ADA4410). Also, the S-
video signals are recombined to form the composite output signal (Cvid out).
The outputs of this part are series terminated with 75ohms before going to
L133 (component IO) & L114 (video IO) via L121 (connection PCB).
Sheet 9 shows the 5 HDMI inputs.
The serial data differential pairs are multiplexed with IC901 & IC903
(PI3HDMI413). The DDC lines are multiplexed with IC907 & IC910
(DG408LDY) for connection with the dual port EEPROM (IC909) and the
HDMI receiver (IC201).
The CEC line is multiplexed with IC911 (DG408DLY)
The +5V line is multiplexed with IC912 (DG408DLY)
Hotplug out is controlled by IC900, IC904 & IC906 (74HCT08 AND gate)
which give individual hotplug control & also global control with PW338
hotplug.
All these multiplexes must operate together for an HDMI input to be correctly
selected.
TMDS Mux
Sel3 Sel2 Sel1 Sel0
0 0 0 0 SAT
0 0 0 1 AV
0 0 1 0 DVD
0 1 1 1 PVR
1 0 1 1 VCR
1 1 1 1 Blank
DDC/CEC/+5V Mux
Sel2 Sel1 Sel0
0 0 0 Blank
0 0 1 AV
0 1 0 SAT
1 1 1 DVD
0 1 1 VCR
1 1 1 PVR
Hotplug Mux
SelPVR SelVCR SelDVD SelSAT SelAV
0 0 0 0 0 Blank
0 0 0 0 1 AV
0 0 0 1 0 SAT
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