7 System
7.1 Resets
The ESP32-S3 has support for four levels of reset:
CPU: resets CPU0/CPU1 core
Core: resets the digital system, except for the RTC peripherals (ULP coprocessor, RTC memory).
System: resets the entire digital system, including the RTC peripherals.
Chip: resets the entire chip.
It is possible to conduct a software reset of this board, as well as obtaining the reset reason.
To do a hardware reset of the board, use the onboard reset button (PB1).
7.2 Timers
The Nano ESP32 has the following timers:
52-bit system timer with 2x 52-bit counters (16 MHz) and 3x comparators.
4x general-purpose 54-bit timers
3x watchdog timers, two in main system (MWDT0/1), one in the RTC module (RWDT).
7.3 Interrupts
All GPIOs on the Nano ESP32 can be configured to be used as interrupts, and is provided by an interrupt matrix.
Interrupt pins are configured on an application level, using the following configurations:
LOW
HIGH
CHANGE
FALLING
RISING