ARTERY AT32A403ACGT7 - User Manual

AT32A403A Series Reference Manual
2022.11.11 Page 1 Rev 2.00
ARM
®
-based 32-bit Cortex
®
-M4F MCU+FPU with 256 to 1024 KB Flash, sLib,
USB, 2 CANs, 17 timers, 3 ADCs, 20 communication interfaces
Feature
 Core: ARM
®
32-bit Cortex
®
-M4F CPU with FPU
− 200 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− Floating Point Unit (FPU)
− DSP instructions
 Memories
− 256 to 1024 KBytes of Flash memory
− sLib: configure any part of main Flash as a library
area that is code executable but secured and non-
readable
− SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
− Up to 96 + 128 KBytes of SRAM
− External memory controller (XMC) with 2 Chip
Select, supporting multiplexed SRAM/NOR/PSRAM
and NAND memories
− LCD parallel interface, 8080/6800 modes
 Clock, Reset, and Power management
− 2.6 V ~ 3.6 V application supply and I/Os
− Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
− 4 to 25 MHz crystal (HEXT)
− Internal 48 MHz factory-trimmed RC (accuracy 1%
at T
A
=25 °C, 2.5 % at T
A
=-40 to +105 °C), with
automatic clock calibration (ACC)
− Internal 40 kHz RC oscillator (LICK)
− 32.768 kHz crystal oscillator (LEXT)
 Low power consumption
− Sleep, Deepsleep, and Standby modes
− V
BAT
supply for RTC and 42 x 16-bit battery powered
registers (BPR)
 3 x 12-bit 0.5 μs A/D converters, up to 16 channels
− Conversion range: 0 V to 3.6 V
− Triple sample and hold capability
− Temperature sensor
 2 x 12-bit D/A converters
 DMA: 14-channel DMA controller
− Peripherals supported: timers, ADCs, SDIOs,
I
2
Ss, SPIs, I
2
Cs, and USARTs
 Debug Mode
− Serial wire debug (SWD) and JTAG interface
− Cortex
®
-M4F Embedded Trace Macrocell (ETM
TM
)
 Up to 80 Fast I/O Interfaces
− 37/51/80 multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
− All fast I/Os, control registers accessible with f
AHB
speed
 Up to 17 Timers
− Up to 8 x 16-bit general-purpose timers + 2 x 32-bit
general-purpose timers; each with 4 IC/OC/PWM or
pulse counter and quadrature (incremental) encoder
input.
− Up to 2 x 16-bit motor control PWM advanced timers
with dead-time generator and emergency brake
− 2 x Watchdog timers
− SysTick timer: 24-bit downcounter
− 2 x 16-bit basic timers to drive the DAC
 Up to 20 Communication Interfaces
− Up to 3 x I
2
C interfaces (SMBus/PMBus)
− Up to 8 x USARTs (ISO7816 interface, LIN, IrDA
capability, and modem control)
− Up to 4 x SPIs (50 Mbit/s), all with I
2
S interface
multiplexed, I
2
S2/ I
2
S3 support full-duplex
− Up to 2 x CAN interfaces (2.0B Active)
− USB2.0 full-speed interface supporting Crystal-less
− Up to 2 x SDIO interfaces
 CRC Calculation Unit
 96-bit unique ID (UID)
 Packages
− LQFP100 14x14 mm
− LQFP64 10x10 mm
− LQFP48 7x7 mm
− QFN48 6 x 6 mm
 List of Models
AT32A403A series: AEC-Q100 Grade 2 certified
Internal Flash
Model
1024 KBytes
AT32A403ACGU7, AT32A403ACGT7,
AT32A403ARGT7, AT32A403AVGT7
512 KBytes
AT32A403ACEU7, AT32A403ACET7,
AT32A403ARET7, AT32A403AVET7
256 KBytes
AT32A403ACCU7, AT32A403ACCT7,
AT32A403ARCT7, AT32A403AVCT7

Summary

System Architecture

Memory Resources

Flash Memory

Describes the on-chip Flash memory organization, including banks, sectors, and sizes.

Power Control (PWC)

Power Saving Modes

Explains Sleep, Deepsleep, and Standby modes for reducing power consumption.

Clock and Reset Manage (CRM)

Clock

Introduces the various clock sources available, including HEXT, HICK, PLL, LEXT, and LICK oscillators.

Flash Memory Controller (FLASH)

Flash Memory Introduction

Introduces the Flash memory organization, including main Flash, external memory, and information block.

Flash Memory Operation

Details the operations for Flash memory, including unlock/lock, erase, programming, and read operations.

User System Data Area Operation

Describes the protection, unlock/lock, erase, and programming operations for the user system data area.

Flash Memory Protection

Covers access protection and erase/program protection mechanisms for Flash memory.

Flash Memory Registers

Lists the Flash memory register map and their reset values.

General-purpose I;Os (GPIOs)

GPIO Registers

Provides a map of GPIO registers and their reset values, accessed by words.

Multiplexed Function I;Os (IOMUX)

IOMUX Registers

Lists the IOMUX register map and their reset values.

External Interrupt;Event Controller (EXINT)

EXINT Introduction

Introduces the EXINT controller, detailing interrupt lines and edge detection capabilities.

Function Overview and Configuration Procedure

Explains how to configure EXINT for GPIO external interrupts and internal sources.

DMA Controller (DMA)

Introduction

Describes the DMA controller's role in enhancing system performance and reducing interrupt generation.

Function Overview

Details DMA configuration steps, channel priority, data transfer direction, and circular mode.

DMA Registers

Provides a map of DMA registers and their reset values.

CRC Calculation Unit (CRC)

CRC Functional Description

Explains the CRC calculation principle, procedure, and parameters like generator polynomial and initial value.

I2 C Interface

I2 C Introduction

Introduces the I2C bus interface for microcontroller communication, supporting master and slave modes.

I2 C Main Features

Lists key features of the I2C interface, including modes, speeds, and protocol support.

I2 C Interface

Details the I2C clock and operation modes, including master and slave interactions.

Universal Synchronous;Asynchronous Receiver;Transmitter (USART)

USART Introduction

Introduces the USART as an interface for communication with various data formats and protocols.

USART Main Features

Lists key features of the USART, including communication modes, baud rate, and frame format.

Mode Selector

Baud Rate Generation

Serial Peripheral Interface (SPI)

SPI Introduction

Introduces the SPI interface, supporting SPI and I2S protocols, and configuration procedures.

SPI Description

Transmitter

Receiver

Timer

Basic Timer (TMR6 and TMR7)

General-Purpose Timer (TMR2 to TMR5)

Describes general-purpose timers (TMR2-TMR5) supporting various counting modes and channels.

General-Purpose Timer (TMR9 to TMR14)

Advanced-Control Timers (TMR1 and TMR8)

Introduces advanced-control timers (TMR1, TMR8) with 16-bit counter supporting various modes and channels.

Window Watchdog Timer (WWDT)

WWDT Introduction

Introduces the window watchdog downcounter for preventing system reset due to malfunctions.

WWDT Main Features

Watchdog Timer (WDT)

WDT Introduction

Introduces the WDT driven by a low-speed clock (LICK) for applications requiring lower timing accuracy.

WDT Main Features

Real-time Clock (RTC)

RTC Introduction

Introduces the RTC as a calendar clock function with an internal 32-bit incremental counter.

RTC Main Features

RTC Functional Overview

Battery Powered Registers (BPR)

BPR Introduction

Analog-to-Digital Converter (ADC)

ADC Introduction

Introduces the ADC peripheral for converting analog signals to 12-bit digital signals with a sampling rate up to 2 MSPS.

ADC Main Features

ADC Functional Overview

ADC Operation Process

Describes the basic operation process of the ADC, including power-on, calibration, trigger, conversion, and data read.

ADC Registers

Digital-to-Analog Converter (DAC)

DAC Introduction

Introduces the DAC peripheral for generating analog output between 0 and reference voltage.

DAC Main Features

CAN

CAN Introduction

Introduces the CAN controller as a serial communication protocol for real-time data.

CAN Main Features

Function Overview

Describes the CAN controller's general features, including filtering mechanisms, FIFOs, and transmit mailboxes.

Message Filtering

Explains how received messages are filtered by identifier and stored in FIFOs or discarded.

Message Transmission

External Memory Controller (XMC)

XMC Introduction

Introduces the XMC peripheral block for translating AHB signals into external memory signals.

XMC Main Features

NOR;PSRAM

Details NOR/PSRAM features, operation modes, pin functions, and access timings.

NAND

Describes the NAND interface, operation modes, pin functions, and access timings.

XMC Registers

SDIO Interface

SDIO Introduction

Introduces the SDIO interface for connecting to MMC, SD memory cards, and SDIO cards.

SDIO Main Features

Card Functional Description

Commands and Responses

Universal Serial Bus Full-Speed Device Interface (USBFS)

USBFS Introduction

Introduces the USBFS implementing USB2.0 full-speed protocols, supporting various transfer types and low-power states.

USBFS Clock and Pin Configuration

Endpoint Configuration

Describes endpoint configuration, including number, transfer type, buffer allocation, and toggle status.

USB Buffer

HICK Auto Clock Calibration (ACC)

ACC Introduction

Introduces HICK auto clock calibration using SOF signals for HICK clock sampling and calibration.

Main Features

Lists key features of ACC, including programmable frequency, boundary settings, and calibration modes.

Functional Description

Explains the auto clock calibration process, its purpose for USB applications, and the cross-return algorithm.

Debug (DEBUG)

Debug Introduction

ARTERY AT32A403ACGT7 Specifications

General

Series	AT32
Core Processor	ARM Cortex-M4
Core Size	32-Bit
Max CPU Frequency	240 MHz
SRAM	32 KB
GPIO	37
DAC	No
Mounting Type	Surface Mount
Operating Voltage	2.6V to 3.6V
Package	LQFP48
Operating Temperature	-40°C to 85°C
ADC	16-channel, 12-bit
Timers	10
Communication Interfaces	3x UART, 3x SPI, 2x I2C
Connectivity	CAN, USB
Peripherals	DMA, RTC, CRC
Oscillator Type	Internal and External