ARTERY AT32F413 Series - User Manual

AT32F413 Series Reference Manual
2022.06.27 Page 1 Rev 2.00
ARM
®
-based 32-bit Cortex
®
-M4F MCU+FPU with 64 to 25 KB Flash, sLib,
USB, 2 CANs, 12 timers, 3 ADCs, 13 communication interfaces
Feature
 Core: ARM
®
32-bit Cortex
®
-M4F CPU with FPU
− 200 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− Floating Point Unit (FPU)
− DSP instructions
 Memories
− 64 to 256 KBytes of Flash memory
− sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
− SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
− Up to 64 KBytes of SRAM
 Clock, Reset, and Power management
− 2.6 V ~ 3.6 V application suppy and I/Os
− Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
− 4 to 25 MHz crystal (HEXT)
− Internal 48 MHz factory-trimmed RC (accuracy 1%
at T
A
=25 °C, 2.5 % at T
A
=-40 to +105 °C), with
automatic clock calibration (ACC)
− Internal 40 kHz RC oscillator (LICK)
− 32.768 kHz crystal oscillator (LEXT)
 Low power consumption
− Sleep, Deepsleep, and Standby modes
− V
BAT
supply for RTC and 42 x 16-bit battery powered
registers (BPR)
 2 x 12-bit 0.5 μs A/D converters, up to 16 channels
− Conversion range: 0 V to 3.6 V
− Dual sample and hold capability
− Temparature sensor
 DMA: 12-channel DMA controller
− Peripherals supported: timers, ADCs, SDIOs,
I
2
Ss, SPIs, I
2
Cs, and USARTs
 Debug mode
− Serial wire debug (SWD) and JTAG interface
 Up to 55 fast I/O Interfaces
− 27/39/55 multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
− All fast I/Os, control registers accessable with f
AHB
speed
 Up to 12 Timers
− Up to 5 x 16-bit timers + 2 x 32-bit timers; each with 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input.
− Up to 2 x 16-bit motor control PWM advanced timers
with dead-time generator and emergency brake
− 2 x Watchdog timers
− SysTick timer: 24-bit downcounter
 Up to 13 Communication Interfaces
− Up to 2 x I
2
C interfaces (SMBus/PMBus)
− Up to 5 x USARTs (ISO7816 interface, LIN, IrDA
capability, and modem control)
− Up to 2 x SPIs (can be used as I
2
S)
− Up to 2 x CAN interfaces (2.0B Active)
− USB2.0 full-speed interface supporting Crystal-less
− SDIO
 CRC Calculation Unit
 96-bit unique ID (UID)
 Packages
− LQFP64 10x10 mm
− LQFP64 7x7 mm
− QFN48 6 x 6 mm
− QFN32 4x4 mm
 List of Models
Internal Flash
Model
256 KBytes
AT32F413RCT7, AT32F413CCT7,
AT32F413CCU7, AT32F413KCU7
128 KBytes
AT32F413RBT7, AT32F413CBT7,
AT32F413CBU7, AT32F413KBU7
64 KBytes
AT32F413C8T7

Summary

System architecture

System overview

Provides an overview of the AT32F413 series microcontrollers, covering core features, peripherals, and architecture.

ARM Cortex-M4 F processor

Details the features of the ARM Cortex-M4F processor, including its DSP instructions and FPU support.

Memory resources

Internal memory address map

Illustrates the memory address mapping for Flash, SRAM, and peripheral registers within the microcontroller.

Flash memory

Describes the organization and architecture of the on-chip Flash memory, including bank configurations.

Power control (PWC)

Introduction

Introduces the power supply, temperature range, and power-saving modes of the AT32F413 series microcontrollers.

Main Features

Highlights key features of the power control unit, including power domains, saving modes, and voltage detection.

Clock and reset management (CRM)

Clock

Details the various clock sources available, including HEXT, HICK, PLL, LEXT, and LICK oscillators.

System clock

Explains the system clock selection and switching mechanism among HICK, HEXT, and PLL clocks.

CRM registers

Clock control register (CRM_CTRL)

Describes the CRM_CTRL register bits for controlling clock sources, bypass modes, and calibration.

Clock configuration register (CRM_CFG)

Clock output selection

Explains how to select the clock output source for the CLKOUT pin, including various peripheral clocks.

Clock interrupt register (CRM_CLKINT)

Clock failure detection flag clear

Details the CFDFC bit for clearing the clock failure detection flag and enabling interrupt requests.

APB2 peripheral reset register (CRM_APB2 RST)

ACC reset

Describes the ACC reset bit, which enables resetting the ACC peripheral.

APB1 peripheral reset register (CRM_APB1 RST)

CAN2 reset

Details the CAN2 reset bit, allowing software to reset the CAN2 peripheral.

APB peripheral clock enable register (CRM_AHBEN)

SDIO1 clock enable

Describes the SDIO1EN bit for enabling the SDIO1 clock in normal, Sleep, or Deepsleep modes.

APB2 peripheral clock enable register (CRM_AHB2 EN)

ACC clock enable

Controls the ACC clock enable, allowing it to be enabled or disabled.

APB1 peripheral clock enable register (CRM_AHB1 EN)

CAN2 clock enable

Enables or disables the clock for the CAN2 peripheral.

Battery powered domain control register (CRM_BPDC)

RTC clock enable

Controls the RTC clock enable, allowing it to be enabled or disabled.

Control;status register (CRM_CTRLSTS)

Low-power reset flag

Indicates if a low-power reset has occurred, cleared by writing to RSTFC bit.

Additional register1 (CRM_MISC1)

Clock output division

Allows setting the frequency division of the CLKOUT signal, providing flexibility in clock output.

Additional register3 (CRM_MISC3)

Auto step-by-step system clock switch enable

Enables automatic system clock switching, ensuring smooth transitions between clock sources.

Flash memory controller (FLASH)

Flash memory introduction

Provides an introduction to the Flash memory, detailing its structure, capacity, and page organization.

Flash memory operation

Unlock;lock

Describes the procedure for unlocking and locking the Flash memory block for programming operations.

Programming operation

Flash memory programming process

Details the step-by-step process for programming the Flash memory, including checks and data writing.

User system data area operation

Unlock;lock

Explains how to unlock and lock the user system data area for programming operations.

Flash memory protection

Access protection

Covers Flash memory access protection, detailing allowed operations and conditions for enabling/disabling.

Special functions

Security library settings

Describes the security library, its protection mechanisms, advantages, and configuration steps.

Flash memory registers

Flash performance select register (FLASH_PSR)

Details the FLASH_PSR register, which is reserved and kept at its default value.

General-purpose I;Os (GPIOs)

Introduction

Introduces General-purpose I/Os (GPIOs), their grouping, main features, and support for multiplexed functions.

GPIO registers

GPIO configuration register low (GPIOx_CFGLR)

Defines the GPIOx configuration register low bits for setting GPIO function and mode.

Multiplexed function I;Os (IOMUX)

Introduction

Introduces multiplexed function I/Os (IOMUX) and their support for various peripherals.

IOMUX registers

Event output control register (IOMUX_EVTOUT)

Controls the event output functionality, allowing redirection of Cortex-M EVENTOUT signal to I/O pins.

IOMUX remap register (IOMUX_REMAP)

SPI1 IO multiplexing

Configures SPI1 IO multiplexing, allowing selection of different pins for SPI communication.

External interrupt;Event controller (EXINT)

EXINT introduction

Introduces the EXINT controller, its interrupt lines, and edge/software trigger capabilities.

DMA controller (DMA)

Introduction

Explains the DMA controller's role in enhancing system performance by managing peripheral access requests.

DMA registers

DMA channelx configuration register (DMA_CxCTRL)

Configures DMA channel settings including priority, transfer direction, address increment, and circular mode.

CRC calculation unit (CRC)

CRC introduction

Introduces the Cyclic Redundancy Check (CRC) peripheral, following the CRC32 standard.

I2 C interface

I2 C introduction

Introduces the I2C bus interface for microcontroller communication, supporting master and slave modes.

I2 C interface

I2 C clock

Explains how the I2C clock is achieved by setting CLKFREQ bits in the I2C_CTRL2 register.

I2 C registers

Control register1 (I2 C_CTRL1)

Describes the I2C_CTRL1 register, covering peripheral reset, SMBus alert, PEC transfer, master acknowledge, and GENSTOP/GENSTART bits.

Universal synchronous;asynchronous receiver;transmitter (USART)

USART introduction

Introduces the USART peripheral, its capabilities for synchronous and asynchronous communication, and supported protocols.

Universal synchronous;asynchronous receiver;transmitter (USART)

Mode selector

Explains the USART mode selector for operating in different modes like LIN, Smartcard, Infrared, and Synchronous.

Serial peripheral interface (SPI)

SPI description

Describes the SPI interface, its configurations (host/slave, full/half-duplex), DMA transfer, and CRC function.

I2 S functional description

I2 S introduction

Introduces the I2S interface, its configuration as master/slave for reception/transmission, and supported audio protocols.

Timer

TMR functional comparison

Provides a comparison of timer functionalities, including counter bit, mode, prescaler, and interrupt capabilities.

General-purpose timer (TMR2 to TMR5)

TMRx introduction

Introduces the general-purpose timer (TMR2 to TMR5), its counting modes, capture/compare registers, and PWM output.

TMRx registers

TMR1 and TMR8 registers

Lists the registers for TMR1 and TMR8, including control, status, and channel mode registers.

General-purpose timer (TMR9 to TMR11)

TMRx main features

Details the main features of general-purpose timers TMR9 and TMR12, including clock sources and channels.

General-purpose timer (TMR9 to TMR11)

TMRx functional overview

Explains the count clock sources for general-purpose timers, including internal, external, and internal trigger inputs.

TMR9 registers

Control register1 (TMR9_CTRL1)

Describes the TMR9_CTRL1 register bits for clock division, period buffer, counting mode, and overflow event source.

TMR9 registers

Slave timer control register (TMR9_STCTRL)

Configures the slave timer mode, input selection, and synchronization with the master timer.

TMR9 registers

Interrupt status register (TMR9_ISTS)

Provides the interrupt status flags for TMR9 channels, including recapture and trigger interrupt flags.

Advanced-control timers (TMR1 and TMR8)

TMR1 and TMR8 introduction

Introduces the advanced-control timers TMR1 and TMR8, highlighting their 16-bit counter and capture/compare features.

Window watchdog timer (WWDT)

WWDT introduction

Introduces the window watchdog timer, its purpose for preventing system resets, and its clock source.

Window watchdog timer (WWDT)

WWDT registers

Lists the WWDT registers, including control, configuration, and status registers.

Watchdog timer (WDT)

WDT introduction

Introduces the WDT, its low-speed clock source (LICK), and suitability for low-timing accuracy applications.

Real-time clock (RTC)

RTC introduction

Introduces the RTC as a calendar clock function with an internal 32-bit incremental counter.

Real-time clock (RTC)

RTC functional overview

Details the RTC functional overview, including register configuration, synchronization logic, and reset behavior.

RTC registers

RTC control register high (RTC_CTRLH)

Describes the RTC_CTRLH register bits for enabling overflow, alarm, and second interrupts.

Battery powered registers (BPR)

BPR introduction

Introduces battery powered registers located in the battery powered domain, powered by VDD/VBAT.

Analog-to-digital converter (ADC)

ADC introduction

Introduces the ADC peripheral, its function of converting analog signals to digital, sampling rate, and channel count.

ADC functional overview

Channel management

Details channel management for ADCs, including analog signal channel inputs and channel conversion groups.

ADC operation process

Power-on and calibration

Explains the power-on and calibration process for the ADC, including clock configuration and calibration steps.

ADC operation process

Trigger

Describes ADC trigger mechanisms, including ordinary and preempted channel triggers, software triggers, and external events.

CAN

CAN introduction

Introduces the Controller Area Network (CAN) protocol, its features, and version support.

CAN

General functional description

Provides a general description of the CAN controller, highlighting filtering mechanisms, FIFOs, and identifier support.

Universal serial bus full-seed device interface (USBFS)

USBFS introduction

Introduces the USBFS, its implementation of USB2.0 full-speed protocols, bus speed, and endpoint capabilities.

Universal serial bus full-seed device interface (USBFS)

Endpoint configuration

Details the USBFS endpoint configuration, including number, transfer types, buffer allocation, and status.

HICK auto clock calibration (ACC)

ACC introduction

Introduces HICK auto clock calibration (HICK ACC), its purpose for USB clock accuracy, and calibration algorithm.

SDIO interface

SDIO introduction

Introduces the SD/SDIO MMC card host interface, its connection to AHB bus, and compatibility with various card specifications.

SDIO interface

Card functional description

Describes the card functional description, including command types, addressible commands, and operational modes.

Debug (DEBUG)

Debug introduction

Introduces the debug features of Cortex-M4F, including halt, single step, trace, and debug interfaces like SWD and JTAG.

ARTERY AT32F413 Series Specifications

General

Series	AT32F413
Core	ARM Cortex-M4
Flash Memory	Up to 256 KB
SRAM	Up to 32 KB
GPIO Pins	51
ADC	12-bit, up to 16 channels
DAC	12-bit, 2 channels
Timers	Advanced, general-purpose, basic timers
Communication Interfaces	I2C, SPI, USART, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP48, LQFP64
DMA Channels	7