ARTERY AT32F435ZMT7 - User Manual

AT32F435/437 Series Reference Manual
2022.11.11 Page 1 Rev 2.03
ARM
®
-based 32-bit Cortex
®
-M4F MCU+FPU with 256 to 4032 KB Flash, sLib,
dual QSPI, SDRAM, dual OTGFS, Ethernet, camera, 18 timers, 3 ADCs, 23
communication interfaces
Feature
 Core: ARM
®
32-bit Cortex
®
-M4F CPU with FPU
− 288 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− Floating Point Unit (FPU)
− DSP instructions
 Memories
− 256 to 4032 KBytes of Flash memory
− sLib: configurable part of main Flash set as a library
area with code executable but secured, non-
readable
− 384 to 512 KBytes of SRAM
− External memory controller (XMC) with 16-bit data
bus: supports CF, SRAM, PSRAM, NOR, NAND,
SDRAM memories
− Up to 2 x QSPI interfaces for external SPI Flash or
SPI RAM extension, and memory mapping mode
 LCD parallel interface, 8080/6800 modes
 Power control (PWC)
− 2.6 V ~ 3.6 V application supply
− Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
− Low power: Sleep, Deepsleep, and Standby modes
− VBAT supply for LEXT, ERTC and 20 x 32-bit battery
power register (ERTC_BPR)
 Clock and reset management (CRM)
− 4 to 25 MHz crystal oscillator (HEXT)
− Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at T
A
=25 °C, 2.5 % at T
A
=-40 to
+105 °C, with automatic clock calibration (ACC)
− PLL with configurable frequency multiplication and
division factor
− 32.768 kHz crystal oscillator (LEXT)
− Internal 40 kHz RC oscillator (LICK)
 Analog
− 3 x 12-bit 5.33 MSPS A/D converters, up to 24 input
channels, 12-bit/10-bit/8-bit/6-bit configurable
resolution
− Temperature sensor (V
TS
), internal reference
voltage (V
INTR
), V
BAT
battery voltage monitor
(V
BAT
/4)
− 2 x 12-bit D/A converters
 DMA:
− 2 x general-purpose DMAs and 1 x EDMA
− 22 channels in all
 Up to 116 Fast I/O Interfaces
− All mappable to 16 external interrupt vectors
− Almost 5 V-tolerant
 Up to 18 Timers (TMR)
− Up to 13 x 16-bit timers + 2 x 32-bit timers, each with 4
IC/OC/PWM or pulse counter channels
− 2 x Watchdog timers (WDT and WWDT)
− SysTick timer: 24-bit downcounter
 ERTC: enhanced RTC with auto wakeup, alarm,
subsecond precision, hardware calendar and
calibration feature
 Up to 23 communication interfaces
− Up to 3 x I
2
C interfaces (SMBus/PMBus)
− Up to 4 x USARTs/4 x UARTs (ISO7816 interface, LIN,
IrDA capability, modem control and RS485 drive enable,
with interchangeable TX/RX)
− Up to 4 x SPIs (36 Mbit/s), all with I
2
S interface
multiplexed, I
2
S2/ I
2
S3 support full-duplex
− Up to 2 x CAN interfaces (2.0B Active)
− Up to 2 x OTG FS controllers supporting crystal-less
− Up to 2 x SDIO interfaces
− Infrared transmitter (IRTMR)
− 10/100M Ethernet MAC with dedicated DMA and
SRAM(4 Kbytes): IEEE1588 hardware support, MII/RMII
available (For AT32F437 only)
 8~14 bit parallel digital camera interface (DVP)
 CRC Calculation Unit
 96-bit ID (UID)
 Debug mode
− SWD and JTAG interfaces
 Temperature range: -40 to 105℃
 Packaging
− LQFP144 20 x 20 mm LQFP100 14 x 14 mm
− LQFP64 10 x 10 mm LQFP48 7 x 7 mm
− QFN48 6 x 6 mm
 List of Models
Internal Flash
Model
4032 KBytes
AT32F435ZMT7, AT32F435VMT7
AT32F435RMT7, AT32F435CMT7
AT32F435CMU7, AT32F437ZMT7,
AT32F437VMT7 AT32F437RMT7
1024 KBytes
AT32F435ZGT7, AT32F435VGT7,
AT32F435RGT7 AT32F435CGT7,
AT32F435CGU7, AT32F437ZGT7
AT32F437VGT7, AT32F437RGT7
256 KBytes
AT32F435ZCT7 AT32F435VCT7
AT32F435RCT7 AT32F435CCT7
AT32F435CCU7 AT32F437ZCT7
AT32F437VCT7 AT32F437RCT7

Summary

System Architecture

Memory Resources

Details the internal memory map, Flash memory organization, and SRAM memory.

Power Control (PWC)

Explains power supply domains, power saving modes, and power voltage monitoring features.

Clock and Reset Management (CRM)

Covers clock sources, system clock configuration, and reset mechanisms.

Flash Memory Controller

Flash Memory Operation

Describes unlock/lock procedures, erase, and programming operations for Flash memory.

Flash Memory Protection

Explains access and erase/program protection mechanisms for Flash memory.

GPIOs and IOMUX

GPIO Registers

Provides register map and reset values for GPIO configuration.

External Interrupt;Event Controller (EXINT)

Function Overview and Configuration Procedure

Describes EXINT lines, edge detection modes, trigger modes, and configuration steps.

DMA Controller (DMA)

DMA Registers

Lists DMA register maps and their reset values for control and status.

I2 C Interface

I2 C Main Features

Details I2C bus capabilities including master/slave modes, speed, addressing, and SMBus support.

I2 C Interface

I2 C Registers

Provides the I2C register map and reset values for configuration.

Universal Synchronous;Asynchronous Receiver;Transmitter (USART)

USART Main Features

Mode Selector

Baud Rate Generation

Explains the baud rate generator and configuration for desired baud rates.

Receiver Configuration

Serial Peripheral Interface (SPI)

Function Overview

Provides an introduction to SPI features, configuration procedures, and modes.

Chip Select Controller

DMA Transfer

Transmitter

Receiver

Timer

Basic Timer (TMR6 and TMR7)

Covers basic timer introduction, main features, function overview, and registers.

General-purpose Timer (TMR2 to TMR5)

Details general-purpose timer features, functional overview, and registers.

General-purpose Timer (TMR9 to TMR14)

Describes general-purpose timers TMR9 to TMR14 features and functional overview.

Advanced-control Timers (TMR1,TMR8 and TMR20)

Covers advanced timers introduction, main features, and functional overview.

Window Watchdog Timer (WWDT)

WWDT Main Features

WWDT Registers

Provides the WWDT register map and reset values for configuration.

Watchdog Timer (WDT)

WDT Main Features

WDT Registers

Provides the WDT register map and reset values for configuration.

Enhanced Real-Time Clock (ERTC)

ERTC Main Features

ERTC Function Overview

ERTC Registers

Lists the ERTC register map and reset values for configuration.

Analog-to-Digital Converter (ADC)

ADC Main Features

ADC Functional Overview

Master;Slave Mode

ADC Registers

Provides the ADC register map and reset values for configuration.

Digital-to-Analog Converter (DAC)

DAC Main Features

DAC Registers

Lists the DAC register map and reset values for configuration.

CAN

CAN Main Features

Baud Rate

Explains the CAN baud rate calculation and formula.

Message Filtering

Details CAN message filtering mechanisms including filter bit width and modes.

Message Transmission

Message Reception

CAN Registers

Provides the CAN register map and reset values for configuration.

Universal Serial Bus Full-Speed Device Interface (OTGFS)

OTGFS Clock and Pin Configuration

OTGFS Functional Description

OTGFS Device Mode

Details device mode operations including initialization, endpoint setup, and transfers.

OTGFS Host Mode

Covers host mode registers, configuration, and transfer operations.

HICK Auto Clock Calibration (ACC)

Register Description

Provides ACC register map and reset values for configuration.

External Memory Controller (XMC)

XMC Main Features

NOR;PSRAM

NAND Flash

SDRAM Card

XMC Registers

Lists the XMC register map and reset values for configuration.

SDIO Interface

Functional Description

SDIO Registers

Provides the SDIO register map and reset values for configuration.

Ethernet Media Access Control (EMAC)

EMAC Main Features

EMAC Functional Description

EMAC Frame Communication

Ethernet Frame Transmission and Reception using DMA

Explains transmission and reception of Ethernet frames scheduled through DMA.

EMAC Registers

Provides the Ethernet register map and reset values for configuration.

Digital Video Parallel Interface (DVP)

Data Capture and Synchronization

Explains data capture using DVP pixel clock and synchronization modes.

DMA Access Interface and Data Output Packing

Registers

Provides the DVP register map and reset values for configuration.

Qud-SPI Interface (QSPI)

QSPI Command Slave Port

SPI Device Operation

QSPI Registers

Provides the QSPI register map and reset values for configuration.

EDMA Controller (EDMA)

Main Features

Functional Overview

DMA Multiplexer (DMAMUX)

Covers DMAMUX overview, channel control, synchronization, and interrupt registers.

EDMA Registers

Provides the EDMA register map and reset values for configuration.

ARTERY AT32F435ZMT7 Specifications

General

Brand	ARTERY
Model	AT32F435ZMT7
Category	Computer Hardware
Language	English