AT32F435/437 Series Reference Manual
2022.11.11 Page 577 Rev 2.03
Supports checking IPv4 header checksum and IPv4, TCP, UDP or ICMP (packaged in IPv4 or
IPv6 data formats) checksum
Supports Ethernet frame time stamp as defined in IEEE 1588-2008. 64-bit time stamps are
recorded in the transmit or receive status
Two 2 KB FIFOs: one for transmit, and one for receive with a configurable threshold
Filter received error frames and not forward them to the application in store-forward mode
Supports store-forward mechanism for data transfer to the MAC controller
Discard frames on late collision, excessive collisions, excessive deferral and underflow
conditions
Clear FIFO by software
Calculates and inserts IPv4 header checksum and TCP, UDP or ICMP checksum in frames
transmitted in store-forward mode
Supports loopback mode on the MII interface for debugging
Programmable time stamps of receive and transmit frames as defined in IEEE 1588-2008
standard
Supports two correction methods: coarse and fine correction
Second pulse output (programmable)
Trigger interrupts when the system is greater the specified time
26.2 EMAC functional description
The Ethernet peripheral consists of a MAC 802.3 (media access controller), MII interface and a
dedicated DMA controller.
It implements the following functions:
Data transmit and receive
― Framing (frame boundary and frame synchronization)
― Handling of source and destination addresses
― Error detection
Media access management in half-duplex mode
― Medium allocation (avoid collision)
― Collision resolve (handle collision)
Usually there are two operating modes for the MAC sublayer:
Half-duplex mode: The stations compete for the use of the physical medium using the CSMA/CD
algorithm. Two stations can only communicate in a single transfer direction at the same time.
Full-duplex mode: CSMA/CD algorithm is unnecessary, but the following conditions must be met:
― Physical medium supports simultaneous transmission and reception
― Only two stations connected to the LAN
― Both two stations configured as full-duplex mode
26.2.1 EMAC communication interfaces
The EMAC allows to configure the station management interface (SMI) of PHY, media-independent
interface (MII) for Ethernet frame communication, and reduced media-independent interface RMII.
Station management interface (SMI)
The PHY management interface (SMI) accesses PHY registers through a clock and data line. It
supports up to 32 PHYs.
MDC: PHY configures clock signals, at the maximum frequency of 2.5 MHx. The minimum high and
low times for MDC must be 160ns, and the minimum period is 400ns. In idle state, the MDC clock signal
remains low.
MDIO: Bidirectional port, data input/output lines.
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