ARTERY AT32F435ZMT7 - TMR1, TMR8 and TMR20 DMA Data Register (Tmrx_Dmadt); TMR1, TMR8 and TMR20 Channel Mode Register3 (Tmrx_ CM3); TMR1, TMR8 and TMR20 Channel 5 Data Register (Tmrx_C5 Dt)

AT32F435/437 Series Reference Manual
2022.11.11 Page 331 Rev 2.03
14.4.4.20 TMR1, TMR8 and TMR20 DMA data register
(TMRx_DMADT)
Bit
Register
Reset value
Type
Description
Bit 15: 0
DMADT
0x0000
rw
DMA data register
A write/read operation to the DMADT register accesses
any TMR register located at the following address:
TMRx peripheral address + ADDR*4 to TMRx peripheral
address + ADDR*4 + DTB*4
14.4.4.21 TMR1, TMR8 and TMR20 channel mode register3 (TMRx_
CM3)
Bit
Register
Reset value
Type
Description
Bit 15: 6
Reserved
0x000
resd
Kept at its default value.
Bit 7
C5OSEN
0x0
rw
Channel 5 output switch enable
Bit 6: 4
C5OCTRL
0x0
rw
Channel 5 output control
Bit 3
C5OBEN
0x0
rw
Channel 5 output buffer enable
Bit 2
C5OIEN
0x0
rw
Channel 5 output immediately enable
Bit 1: 0
Reserved
0x0
resd
Kept at its default value.
14.4.4.22 TMR1, TMR8 and TMR20 channel 5 data register
(TMRx_C5DT)
Bit
Register
Reset value
Type
Description
Bit 15: 0
C5DT
0x0000
rw
Channel 5 data register
C5DT holds the value that is to be compared with the
CVAL. Whether the written data will takes effect
immediately depends on the C5OBEN bit, and the
corresponding output generates on the C5OUT bit.