ARTERY AT32F435ZMT7 - Figure 24-3 NOR;PSRAM Mode 1 Read Access; Figure 24-4 NOR;PSRAM Mode 1 Write Access; Table 24-14 Mode 2 - SRAM;NOR Flash Chip Select Control Register

AT32F435/437 Series Reference Manual
2022.11.11 Page 511 Rev 2.03
Figure 24-3 NOR/PSRAM mode 1 read access
XMC_NE[x]
XMC_NOE
XMC_NWE
XMC_D[15：0]
Data from external
memory
ADDRST+1
HCLK
DTST+1
HCLK
High
2
HCLK
XMC capture
data
Memory address
High-Z
Don t care
Data signals
Chip select
signal
XMC_A[25：0]
Address signals
XMC_LB
XMC_UB
Figure 24-4 NOR/PSRAM mode 1 write access
XMC_A[25：0]
XMC_NE[x]
XMC_NOE
XMC_NWE
XMC_D[15：0]
1
HCLK
Data from XMC
ADDRST+1
HCLK
DTST+1
HCLK
High
High-Z
Memory address
Don t care
Address signals
Data signals
Chip select
signal
XMC_LB
XMC_UB
Mode 2
As configured in Table 24-14 and Table 24-15, the XMC uses mode 2 to access the external memory.
The timing of read operation is shown in Figure 24-5. The timing of write operation is shown in Figure
24-6.
Table 24-14 Mode 2 — SRAM/NOR Flash chip select control register
Bit
Description
Configuration
Bit 31: 20
Reserved
0x0
Bit 19
MWMC: Memory write mode control
0x0
Bit 18: 16
CRPGS:CRAM page size
0x0
Bit 15
NWASEN: NWAIT in asynchronous
transfer enable
Configure according to memory specifications.