ARTERY AT32F403ACGU7 - User Manual

AT32F403A/407 Series Reference Manual
2021.12.01 Page 1 Ver 2.02
ARM
®
-based 32-bit Cortex
®
-M4F MCU+FPU with 256 to 1024 KB Flash, sLib,
USB, Ethernet, 2 CANs, 17 timers, 3 ADCs, 21 communication interfaces
Feature
 Core: ARM
®
32-bit Cortex
®
-M4F CPU with FPU
− 240 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− Floating Point Unit (FPU)
− DSP instructions
 Memories
− 256 to 1024 KBytes of Flash memory
− sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
− SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
− Up to 96 + 128 KBytes of SRAM
− External memory controller (XMC) with 2 Chip
Select, supports multiplexed SRAM/NOR/PSRAM
and NAND memories
− LCD parallel interface, 8080/6800 modes
 Clock, Reset, and Power management
− 2.6 V ~ 3.6 V application suppy and I/Os
− Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
− 4 to 25 MHz crystal (HEXT)
− Internal 48 MHz factory-trimmed RC (accuracy 1%
at T
A
=25 °C, 2.5 % at T
A
=-40 to +105 °C), with
automatic clock calibration (ACC)
− Internal 40 kHz RC oscillator (LICK)
− 32.768 kHz crystal oscillator (LEXT)
 Low power consumption
− Sleep, Deepsleep, and Standby modes
− V
BAT
supply for RTC and 42 x 16-bit battery powered
registers (BPR)
 3 x 12-bit 0.5 μs A/D converters, up to 16 channels
− Conversion range: 0 V to 3.6 V
− Triple sample and hold capability
− Temparature sensor
 2 x 12-bit D/A converters
 DMA: 14-channel DMA controller
− Peripherals supported: timers, ADCs, SDIOs,
I
2
Ss, SPIs, I
2
Cs, and USARTs
 Debug Mode
− Serial wire debug (SWD) and JTAG interface
− Cortex
®
-M4F Embedded Trace Macrocell (ETM
TM
)
 Up to 80 Fast I/O Interfaces
− 37/51/80 multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
− All fast I/Os, control registers accessable with f
AHB
speed
 Up to 17 Timers
− Up to 8 x 16-bit timers + 2 x 32-bit timers; each with 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input.
− Up to 2 x 16-bit motor control PWM advanced timers
with dead-time generator and emergency brake
− 2 x Watchdog timers
− SysTick timer: 24-bit downcounter
− 2 x 16-bit basic timers to drive the DAC
 Up to 21 Communication Interfaces
− Up to 3 x I
2
C interfaces (SMBus/PMBus)
− Up to 8 x USARTs (ISO7816 interface, LIN, IrDA
capability, and modem control)
− Up to 4 x SPIs (50 Mbit/s), all with I
2
S interface
multiplexed,. I
2
S2/ I
2
S3 support full-duplex
− Up to 2 x CAN interfaces (2.0B Active)
− USB2.0 full-speed interface supporting Crystal-less
− Up to 2 x SDIO interfaces
− 10/100M Ethernet MAC with dedicated DMA and
SRAM(4 KBytes): IEEE1588 hardware support, MII/RMII
available
 CRC Calculation Unit
 96-bit unique ID (UID)
 Packages
− LQFP100 14x14 mm
− LQFP64 10x10 mm
− LQFP48 7x7 mm
− QFN48 6 x 6 mm
 List of Models
Internal Flash
Model
1024 KBytes
AT32F403ACGU7, AT32F403ACGT7,
AT32F403ARGT7, AT32F403AVGT7,
AT32F407RGT7, AT32F407VGT7, AT32F407AVGT7
512 KBytes
AT32F403ACEU7, AT32F403ACET7,
AT32F403ARET7, AT32F403AVET7,
AT32F407RET7, AT32F407VET7
256 KBytes
AT32F403ACCU7, AT32F403ACCT7,
AT32F403ARCT7, AT32F403AVCT7,
AT32F407RCT7, AT32F407VCT7, AT32F407AVCT7

Summary

Feature

Memories

Flash memory (256-1024 KB), SRAM (96+128 KB), external memory interface, XMC controller.

Clock, Reset, and Power management

Operating voltage, POR/LVR, clock sources (HEXT, HICK, LICK), power-on reset, automatic clock calibration.

3 x 12-bit 0.5 μs A;D converters

Up to 16 channels, 0 V to 3.6 V conversion range, triple sample and hold capability.

DMA: 14-channel DMA controller

Supports peripherals like timers, ADCs, SDIOs, I2Cs, SPIs, I2Cs, and USARTs.

Up to 17 Timers

8x 16-bit timers, 2x 32-bit timers; OC/PWM/encoder input support; Motor control timers.

Up to 21 Communication Interfaces

I2C, USART/UART, SPI, CAN, USB2.0, SDIO, Ethernet MAC interfaces.

List of Models

Lists internal flash models and corresponding part numbers.

System architecture

ARM Cortex-M4 F processor

Low power, DSP, FPU support, ARMv7-M architecture, Thumb instruction set.

Interrupt and exception vectors

Table listing interrupt sources, priority, type, name, description, and address.

Memory resources

Internal memory address map

Maps program memory (Flash), data memory (SRAM), and peripheral registers to addresses.

Flash memory

Up to 1024 KB on-chip Flash, zero wait state, single cycle 32-bit read operation.

SRAM memory

Up to 96 KB SRAM, supports byte/half-word/word access, dynamic switch.

Peripheral address map

Maps peripherals to specific address boundaries across AHB and APB buses.

Power control (PWC)

Main Features

Power domains, power saving modes, voltage regulator, power voltage detector, VBAT supply.

POR;LVR

Analog POR module for power reset, VPOR and VLVR reset triggers, hysteresis.

Power voltage monitor (PVM)

Monitors power supply variations, PVMOF bit, hysteresis voltage VHYS_P, PVM interrupt.

Power saving modes

Sleep, Deepsleep, Standby modes; clock slowing and gating for power reduction.

Clock and reset manage (CRM)

Clock

Provides HEXT, HICK, PLL, LEXT, LICK clock sources; AHB/APB clock division.

Clock sources

Details HEXT, HICK, PLL, LEXT, LICK clock sources and their characteristics.

System clock

System clock selection and switching among HICK, HEXT, PLL.

Peripheral clock

Clocks for SysTick, ADCs, Timers, USB, RTC, Watchdog.

Reset

System reset sources (NRST, WDT, WWDT, software, low-power, POR, LVR).

System reset

Lists system reset sources and their effects on registers.

Flash memory controller (FLASH)

Flash memory introduction

Divides Flash memory into main, external, information block, and registers.

Flash memory operation

Details unlock/lock, erase, programming, and read operations.

User system data area operation

Covers unlock/lock, erase, and programming operations for user system data.

Flash memory protection

Discusses access protection and erase/program protection mechanisms.

General-purpose I;Os (GPIOs)

GPIO structure

Describes GPIO pin configuration for input and output modes.

General-purpose input configuration

Configuration for input modes like floating, pull-up/pull-down.

Analog input;output configuration

Configuration for analog input/output modes, disabling digital features.

General-purpose output configuration

Configuration for output modes like Push-Pull and Open-Drain.

I;O port protection

Mechanism to freeze I/O configuration using LOCK.

Multiplex function I;Os (IOMUX)

IOMUX structure

Basic structure of IOMUX, showing interaction with peripherals and GPIO controller.

MUX Input configuration

Configuration for I/O pins as multiplexed function inputs.

MUX output or bidirectional MUX configuration

Configuration for MUX outputs and bidirectional MUX, including remapping.

IOMUX map priority

Priority rules for mapping multiple peripheral functions to the same pin.

IOMUX remap register (IOMUX_REMAP)

Register for SPI1, PTP, SPI3 IO multiplexing, SWD/JTAG, MII/RMII, CAN2, EMAC, ADC2.

IOMUX external interrupt configuration register1 (IOMUX_EXINTC1)

Configures input sources for EXINT3, EXINT2, EXINT1, EXINT0.

IOMUX external interrupt configuration register2 (IOMUX_EXINTC2)

Configures input sources for EXINT7, EXINT6, EXINT5, EXINT4.

IOMUX remap register4 (IOMUX_REMAP4)

Configures IO multiplexing for TMR5, TMR4, TMR3, TMR2.

IOMUX remap register5 (IOMUX_REMAP5)

Configures IO multiplexing for SPI4, SPI3, SPI2, SPI1.

IOMUX remap register6 (IOMUX_REMAP6)

Configures IO multiplexing for UART4, USART3, USART2, USART1, SDIO2, CAN2, CAN1.

IOMUX remap register7 (IOMUX_REMAP7)

Configures XMC_NADV, XMC, PD0/PD1 mapping, SWJTAG, ADC2.

IOMUX remap register8 (IOMUX_REMAP8)

Configures EMAC IO multiplexing.

External interrupt;Event controller (EXINT)

Function overview and configuration procedure

Details EXINT lines, internal sources, and configuration steps.

Interrupt enable register (EXINT_INTEN)

Enables or disables interrupt requests on specific lines.

Event enable register (EXINT_EVTEN)

Enables or disables event requests on specific lines.

Polarity configuration register1 (EXINT_ POLCFG1)

Configures rising edge event detection for interrupt/event lines.

Polarity configuration register2 (EXINT_ POLCFG2)

Configures falling edge event detection for interrupt/event lines.

Software trigger register (EXINT_ SWTRG)

Allows software to generate trigger interrupts.

Interrupt status register (EXINT_ INTSTS)

Provides status of interrupt lines.

DMA controller (DMA)

DMA configuration

Steps to configure DMA, including peripheral/memory addresses and data count.

Programmable data transfer width

Explains PWIDTH and MWIDTH bits for data transfer width configuration.

Interrupts

Describes DMA interrupt sources (half-transfer, complete, error).

Flexible DMA request mapping

Describes programming the request source for each channel using CHx_SRC.

DMA interrupt status register (DMA_STS)

Provides status flags for DMA interrupts (transfer error, half-transfer, complete).

DMA interrupt flag clear register (DMA_CLR)

Register to clear DMA interrupt flags.

DMA channelx configuration register (DMA_CxCTRL)

Configures channel parameters like priority, direction, increment mode, circular mode.

DMA channelx number of data register (DMA_CxDTCNT)

Holds the number of data bytes to be transferred.

DMA channelx peripheral address register (DMA_CxPADDR)

Stores the base address of the peripheral data register.

DMA channelx memory address register (DMA_CxMADDR)

Stores the base address of the memory for data transfer.

Channel source register (DMA_SRC_SEL0)

Selects the source for channels CH1 to CH4.

Channel source register1 (DMA_SRC_SEL1)

Selects the source for channels CH5 to CH7 and enables flexible mapping.

CRC calculation unit (CRC)

Data register (CRC_DT)

Used for inputting data and reading CRC calculation results.

Control register (CRC_CTRL)

Controls CRC calculation unit operation and reset.

I2 C interface

I2 C main features

Lists key I2C features like modes, address modes, interrupts, DMA, SMBus, PMBus.

I2 C function overview

Explains I2C bus protocol with SDA and SCL lines, start/stop conditions.

I2 C interface

Details I2C clocking and operation modes (master/slave).

I2 C clock

Clocking mechanism for I2C, including division and frequency requirements.

Communication process

Details master and slave communication sequences.

Address control

Explains 7-bit and 10-bit addressing modes, including special slave addresses.

Clock stretching capability

Explains clock stretching feature for synchronizing slave data transfer.

I2 C slave communication flow

Step-by-step flow for I2C slave transmitter and receiver operations.

I2 C master communication flow

Step-by-step flow for I2C master transmitter and receiver operations.

I2 C interrupt requests

Lists all I2C interrupt events and their corresponding enable bits.

Control register1 (I2 C_CTRL1)

Controls I2C peripheral reset, SMBus alert, PEC, master acknowledge, stop condition, general call, etc.

Control register2 (I2 C_CTRL2)

Controls DMA transfer, data transfer interrupt, event interrupt, error interrupt, and clock frequency.

Data register (I2 C_DT)

Stores data received or to be transmitted.

Status register1 (I2 C_STS1)

Provides status flags for SMBus alert, timeout, PEC error, overload/underload, ACK fail, arbitration lost, bus error.

Status register2 (I2 C_STS2)

Provides status flags for PEC value, received address, SMBus host/device address, general call address, transmission direction, and bus status.

Clock control register (I2 C_ CLKCTRL)

Configures I2C speed mode, duty cycle, and clock speed.

Universal synchronous;asynchronous receiver;transmitter (USART)

USART main features

Lists features like full/half-duplex, programmable baud rate, frame format, interrupts, DMA, etc.

Configuration procedure

Steps for configuring operation modes like LIN, Smartcard, Infrared, Hardware flow control, Silent, Synchronous.

USART frame format and configuration

Defines USART data frame format, including start/data/stop bits, parity, and break frames.

DMA transfer introduction

Introduction to using DMA for high-speed transmission/reception.

Transmission using DMA

Steps for configuring DMA for USART data transmission.

Reception using DMA

Steps for configuring DMA for USART data reception.

Baud rate generation

Explains USART baud rate generation using internal counter and PCLK.

Transmitter

Details the USART transmitter operation and configuration.

Transmitter configuration

Steps for configuring USART transmitter, including enable, duplex mode, mode, frame format, interrupts, DMA, baud rate.

Receiver

Details the USART receiver operation and configuration.

Receiver configuration

Steps for configuring USART receiver, including enable, duplex mode, mode, frame format, interrupts, DMA, baud rate.

Start bit and noise detection

How start bits and noise are detected using oversampling techniques.

USART interrupt generator

Control center for USART interrupts, mapping interrupt sources to enable bits.

Status register (USART_STS)

Provides status flags for CTS, break frame, transmit buffer, idle line, parity error, noise error, framing error.

Data register (USART_DT)

Holds the data value for read and write operations.

Baud rate register (USART_BAUDR)

Defines the USART divider for baud rate generation.

Control register1 (USART_CTRL1)

Controls USART enable, data bits, wakeup mode, parity, parity selection, interrupts.

Control register2 (USART_CTRL2)

Controls LIN mode, stop bits, clock enable, clock polarity, clock phase, last bit clock pulse, break frame.

Control register3 (USART_CTRL3)

Controls CTS, RTS, DMA, Smartcard, and NACK enable.

Serial peripheral interface (SPI)

SPI description

Details SPI modes, DMA transfer, CRC, frequency, clock polarity/phase.

Full-duplex;half-duplex selector

Selects between full-duplex and half-duplex modes for SPI communication.

Single-wire bidirectional half-duplex mode

Shows IO connection and operation for single-wire bidirectional half-duplex mode.

SPI control register1 (SPI_CTRL1)

Controls single-line modes, CRC calculation, frame bit number, active modes, and CS enable.

SPI control register2 (SPI_CTRL2)

Controls master clock frequency division, transmit/receive interrupts, and error interrupts.

SPI status register (SPI_STS)

Provides status flags for busy, overflow, mode errors, CRC errors, underload, audio channel state, and transmit/receive buffer status.

SPI data register (SPI_DT)

Holds data for read and write operations.

SPI_I2 S register (SPI_I2 SCTRL)

Selects I2S mode, enables I2S, configures operation mode, PCM format, data bits, channel bits.

Timer

Basic timer (TMR6 and TMR7)

Introduction and main features of basic timers, including clock source and upcounter.

TMR6 and TMR7 main features

Lists features like internal clock, 16-bit counter, DAC trigger synchronization, interrupts.

TMR6 and TMR7 function overview

Details count clock, counting modes, and debug mode.

General-purpose timer (TMR2 to TMR5)

Introduction and main features of general-purpose timers.

General-purpose timer (TMR9 to TMR14)

TMRx main features

Lists main features for TMR9/12 and TMR10/11/13/14.

TMR9 and TMR12 main features

TMR10, TMR11, TMR13 and TMR14 main features

TMRx functional overview

Details count clock, counting modes, TMR input function, TMR output function.

Advanced-control timers (TMR1 and TMR8)

Introduction to TMR1 and TMR8 as advanced-control timers with capture/compare.

TMR1 and TMR8 main features

TMR1 and TMR8 functional overview

Count clock

Describes count clock sources for TMR1/TMR8 (internal, external, internal trigger).

Internal clock (CK_INT)

How CK_INT is divided by prescaler for counter clock.

External clock (TRGIN;EXT)

How TRGIN and EXT signals provide counter clock for TMR1/TMR8.

Internal trigger input (ISx)

Timer synchronization using TRGOUT signal and STIS selection.

Counting mode

Explains upcounting, downcounting, up/down counting, repetition counter, and encoder interface modes.

Upcounting mode

Downcounting mode

Up;down counting mode

Encoder interface mode

TMR input function

TMR output function

Window watchdog timer (WWDT)

WWDT main features

WWDT functional overview

Control register (WWDT_CTRL)

Configuration register (WWDT_CFG)

Status register (WWDT_STS)

Watchdog timer (WDT)

WDT main features

WDT functional overview

Command register (WDT_CMD)

Divider register (WDT_DIV)

Reload register (WDT_RLD)

Status register (WDT_STS)

Real-time clock (RTC)

RTC main features

RTC structure

RTC functional overview

Configuring RTC registers

RTC interrupts

RTC control register high (RTC_CTRLH)

RTC control register low (RTC_CTRLL)

RTC divider register (RTC_ DIVH;RTC_DIVL)

Battery powered registers (BPR)

BPR main features

BPR functional overview

Battery powered data register x (BPR_DTx)

BPR control register (BPR_ CTRL)

BPR control;status register (BPR_ CTRLSTS)

Analog-to-digital converter (ADC)

ADC main features

ADC structure

ADC functional overview

Channel management

Internal temperature sensor

Internal reference voltage

ADC operation process

Repetition mode

Partition mode

ADC status register (ADC_STS)

ADC control register1 (ADC_CTRL1)

ADC control register2 (ADC_CTRL2)

Digital-to-analog converter (DAC)

DAC main features

Trigger events

Noise;Triangular-wave generation

DAC control register (DAC_CTRL)

CAN

CAN main features

Baud rate

Interrupt management

Function overview

Overview of CAN controller functionality: filtering, FIFOs, mailboxes, standard/extended identifiers.

Operating modes

Message filtering

CAN control and status registers

CAN master control register (CAN_MCTRL)

CAN master status register (CAN_MSTS)

CAN transmit status register (CAN_TSTS)

CAN receive FIFO 0 register (CAN_RF0)

CAN receive FIFO 1 register (CAN_RF1)

CAN interrupt enable register (CAN_INTEN)

CAN error status register (CAN_ESTS)

CAN bit timing register (CAN_BTMG)

External memory controller

XMC main features

XMC architecture

Address mapping

NOR;PSRAM

Access address

Data access

Access mode

NAND

Operation mode

Describes pin signals for NAND Flash and access address.

Access timings

ECC computation

NOR Flash and PSRAM control registers

SRAM;NOR Flash chip select control register 1 (XMC_BK1 CTRL1)

SRAM;NOR Flash chip select control register 4 (XMC_BK1 CTRL4)

SRAM;NOR Flash chip select timing register 1, 4 (XMC_BK1 TMG1, 4)

SRAM;NOR Flash write timing register 1, 4 (XMC_BK1 TMGWR1, 4)

SRAM;NOR Flash extra timing register 1, 4 (XMC_EXT1, 4)

NAND Flash control registers

NAND Flash control register 2 (XMC_BK2 CTRL)

Regular memory timing register 2 (XMC_BK2 TMGRG)

Special memory timing register 2 (XMC_BK2 TMGSP)

SDIO interface

SDIO main features

Card functional description

Card identification mode

Data transfer mode

Stream read;write (MultiMedia card only)

Data block read

Erase

Protection management

Commands

Response formats

Universal serial bus full-seed device interface (USBFS)

USBFS clock and pin configuration

USB clock configuration

USBFS functional description

USB initialization

Endpoint configuration

USB buffer

Double-buffered endpoints

Suspend;Resume

USBFS interrupts

USBFS endpoint n register (USBFS_EPTn)

USBFS control register (USBFS_CTRL)

HICK auto clock calibration (ACC)

Main features

Lists features: programmable center/boundary frequency, precision, status flags, interrupt sources, calibration modes.

Interrupt requests

Functional description

Principle

Status register (ACC_STS)

Control register 1 (ACC_CTRL1)

Compare value 1 (ACC_C1)

Compare value 2 (ACC_C2)

Compare value 3 (ACC_C3)

Ethernet media access control (EMAC)

EMAC structure

EMAC main features

EMAC frame communication

EMAC frame filtering

Unicast destination address filter

Unicast source address filter

Inverse filtering operation

Ethernet frame transmission and reception using DMA

Ethernet MAC frame transmission and reception using DMA

Ethernet MAC interrupt status register (EMAC_MACISTS)

Ethernet MAC interrupt mask register (EMAC_MAIMR)

Ethernet DMA bus mode register (EMAC_DMABM)

Ethernet DMA transmit poll demand register (EMAC_DMATPD)

Ethernet DMA receive poll demand register (EMAC_DMARPD)

Ethernet DMA receive descriptor list address register (EMAC_DMARDLADDR)

Ethernet DMA status register (EMAC_DMASTS)

Ethernet DMA operation mode register (EMAC_DMAOPM)

Ethernet DMA missed frame and buffer overflow counter register (EMAC_DMAMFBOCNT)

Ethernet DMA current transmit descriptor register (EMAC_DMACTD)

Ethernet DMA current receive descriptor register (EMAC_DMACRD)

Ethernet DMA current transmit buffer address register (EMAC_DMACTBADDR)

Ethernet DMA current receive buffer address register (EMAC_DMACRBADDR)

Ethernet MMC control register (EMAC_MMCCTRL)

Ethernet MMC receive interrupt register (EMAC_MMCRIM)

Ethernet MMC transmit interrupt register (EMAC_MMCTIM)

Ethernet PTP time stamp control register (EMAC_PTPTSCTRL)

Ethernet PTP time stamp addend register (EMAC_PTPTSAD)

Debug (DEBUG)

Debug and Trace

DEBUG control register (DEBUG_CTRL)

ARTERY AT32F403ACGU7 Specifications

General

Microcontroller Core	ARM Cortex-M4
Flash Memory	256 KB
Max Clock/CPU Frequency	120 MHz
Mounting Type	Surface Mount
GPIO Pins	37
ADC Channels	16
ADC Resolution	12 bit
DAC Channels	2
DAC Resolution	12 bit
Operating Voltage	2.6V to 3.6V
Communication Interfaces	I2C, SPI, USART
Operating Temperature	-40°C to +85°C