ARTERY AT32F403ACGU7 - CAN transmit status register (CAN_TSTS)

AT32F403A/407 Series Reference Manual
2021.12.01 Page 331 Ver 2.02
21.7.1.3 CAN transmit status register (CAN_TSTS)
Bit
Register
Reset value
Type
Description
Bit 31
TM2LPF
0x0
ro
Transmit mailbox 2 lowest priority flag
0: Mailbox 2 is not given the lowest priority.
1: Lowest priority (This indicates that more than one
mailboxes are pending for transmission, the mailbox 2 has
the lowest priority.)
Bit 30
TM1LPF
0x0
ro
Transmit mailbox 1 lowest priority flag
0: Mailbox 1 is not given the lowest priority.
1: Lowest priority (This indicates that more than one
mailboxes are pending for transmission, the mailbox 1 has
the lowest priority.)
Bit 29
TM0LPF
0x0
ro
Transmit mailbox 0 lowest priority flag
0: Mailbox 0 is not given the lowest priority.
1: Lowest priority (This indicates that more than one
mailboxes are pending for transmission, the mailbox 0 has
the lowest priority.)
Bit 28
TM2EF
0x1
ro
Transmit mailbox 2 empty flag
This bit is set by hardware when no transmission is
pending in the mailbox 2.
Bit 27
TM1EF
0x1
ro
Transmit mailbox 1 empty flag
This bit is set by hardware when no transmission is
pending in the mailbox 1.
Bit 26
TM0EF
0x1
ro
Transmit mailbox 0 empty flag
This bit is set by hardware when no transmission is
pending in the mailbox 0.
Bit 25: 24
TMNR
0x0
ro
Transmit Mailbox number record
Note:
If the transmit mailbox is free, these two bits refer to the
number of the next transmit mailbox free.
For example, in case of free CAN, the value of these two
bit becomes 01 after a message transmit request is written.
If the transmit box is full, these two bits refer to the number
of the transmit mailbox with the lowest priority.
For example, when there are three messages are pending
for transmission, the identifiers of mailbox 0, mailbox 1 and
mailbox 2 are 0x400, 0x433 and 0x411 respectively, and
the value of these two bits becomes 01.
Bit 23
TM2CT
0x0
ro
Transmit mailbox 2 cancel transmit
0: No effect
1: Transmission is cancelled.
Note: Software sets this bit to abort the transmission of
mailbox 2. This bit is cleared by hardware when the
transmit message in the mailbox 2 is cleared. Setting this
bit has no effect if the mailbox 2 is free.
Bit 22: 20
Reserved
0x0
resd
Kept at its default value.
Bit 19
TM2TEF
0x0
rw1c
Transmit mailbox 2 transmission error flag
0: No error
1: Mailbox 2 transmission error
Note:
This bit is set when the mailbox 2 transmission error
occurred.
It is cleared by software writing 1 or by hardware at the
start of the next transmission
Bit 18
TM2ALF
0x0
rw1c
Transmit mailbox 2 arbitration lost flag
0: No arbitration lost