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AMD X670/B650/A620 Series
RAS# Active Time (tRAS)
e number of clock cycles required between a bank active command and issuing the
precharge command.
RAS# Cycle Time (tRC)
e number of memory clock cycles from activate command to another activate command.
Write Recovery Time (tWR)
e amount of delay that must elapse aer the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC1)
Species the Refresh Recovery Delay Time.
Refresh Cycle Time (tRFC2)
Species the Refresh Recovery Delay Time.
Refresh Cycle Time (tRFCSb)
Species the Refresh Recovery Delay Time.
Read to Precharge (tRTP)
e number of clocks that are inserted between a read command to a row pre-charge
command to the same rank.
RAS to RAS Delay (tRRD_L)
e number of clocks between two rows activated in dierent banks of the same rank.
RAS to RAS Delay (tRRD_S)
e number of clocks between two rows activated in dierent banks of the same rank.
Four Activate Window (tFAW)
Species the time window in which four activates are allowed the same rank.
Write to Read Delay (tWTR_L)
e number of clocks between the last valid write operation and the next read
command to the same internal bank.
Write to Read Delay (tWTR_L)
e number of clocks between the last valid write operation and the next read
command to the same internal bank.
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