ASROCK AMD A620 Series - Page 56

52
L1 Stride Prefetcher
Uses memory access history of individual instructions to fetch additional lines when each
access is a constant distance from the previous.
Conguration options: [Auto] [Disabled] [Enabled]
L1 Region Prefetcher
Uses memory access history to fetch additional lines when the data access for a given
instrction tends to be followed by other data accesses.
Conguration options: [Auto] [Disabled] [Enabled]
L2 Up/Down Prefetcher
Uses memory access history to determine whether to fetch the next or previous line for all
memory accesses.
Conguration options: [Auto] [Disabled] [Enabled]
Core Watchdog
Press [Enter] to congure Core Watchdog options.
Core Watchdog Timer Enable
Allows you to enable or disable CPU Watchdog Timer.
Conguration options: [Auto] [Disabled] [Enabled]
Platform First Error Handling
Allows you to enable or disable PFEH, cloak individual banks, and mask deferred error
interrupts from each bank.
Conguration options: [Auto] [Disabled] [Enabled]
Core Performance Boost
[Disabled] Select this item to disable CPB.
[Auto] BIOS will congure this setting automatically.
Global C-state Control
Allows you to control IO based C-state generation and DF C-state.
Conguration options: [Auto] [Disabled] [Enabled]
Opcache Control
Allows you to enable or disable the Opcache.
Conguration options: [Auto] [Disabled] [Enabled]
Streaming Stores Control
Allows you to enable or disable the streaming stores functionality.
Conguration options: [Auto] [Disabled] [Enabled]
Local APIC Mode
Allows you to select local APIC operation modes.
Conguration options: [Auto] [Compatibility] [xAPIC] [x2APIC]