Asus P5GC - Chipset

ASUS P5GC 4-23
Congure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according to the
DRAM SPD (Serial Presence Detect). When disabled, you can manually set the
DRAM timing parameters through the DRAM sub-items. The following sub-items
appear when this item is Disabled. Conguration options: [Disabled] [Enabled]
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time the
data actually becomes available.
Conguration options: [6 Clock] [5 Clocks] [4 Clocks] [3 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Conguration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5 Clocks] [6 Clocks]
DRAM RAS# to # Delay [4 Clocks]
Controls the latency between the DDR active command and the read/write
command. Conguration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks]
[6 Clocks]
DRAM # Activate to Precharge [15 Clocks]
Conguration options: [4 Clocks] [5 Clocks] ~ [18 Clocks]
DRAM Write Recovery Time [4 Clocks]
Conguration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6 Clocks]
4.4.4 Chipset
The menu allows you to change the advanced chipset settings. Select an item then
press <Enter> to display the sub-menu.
Advanced Chipset Settings
Congure DRAM Timing by SPD [Enabled]
Hyper Path 3 [Auto]
DRAM Throttling Threshold [Auto]
Boot Graphic Adapter Priority [PCI Express/
PCI]
PEG Buffer Length [Auto]
Link Latency [Auto]
PEG Root Control [Auto]
Slot Power [Auto]
High Priority Port Select [Disabled]
Manual DRAM
Frequency Setting or
Auto by SPD
Select Screen
Select Item
+- Change Field
Tab Select Field
F1 General Help
F10 Save and Exit
ESC Exit
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