Atmel 8051 User Manual

Atmel 8051 Microcontrollers Hardware Manual 1-12
Rev. 4316B–8051–02/04
In this example, FLAG is the name of any addressable bit in the lower 128 or SFR
space. An I/O line (the LSB of Port 1, in the case) is set or cleared depending on
whether the flag bit is 1 or 0.
The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean proces-
sor. Bit instructions that refer to the Carry bit as C assemble as Carry-specific
instructions (CLR C, etc.). The Carry bit also has a direct address, since it resides in the
PSW register, which is bit-addressable.
Note that the Boolean instruction set includes ANL and ORL operations, but not the XRL
(Exclusive OR) operation. An XRL operation is simple to implement in software. Sup-
pose, for example, it is required to form the Exclusive OR of two bits:
C= bit1 XRL bit2
The software to do that could be as follows:
MOV C, bit1
JNB bit2, OVER
CPL C
OVER: (continue)
First, bit 1 is moved to the Carry. If bit 2 = 0, then C now contains the correct result. That
is, bit 1 XRL bit2 = bit1 if bit2 = 0. On the other hand, if bit2 = 1 C now contains the com-
plement of the correct result. It need only be inverted (CPL C) to complete the operation.
This code uses the JNB instruction, one of a series of bit-test instructions which execute
a jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is not set (JNC,
JNB). In the above case, bit2 is being tested, and if bit2 = 0 the CPL C instruction is
jumped over.
JBC executes the jump if the addressed bit is set, and also clears the bit. Thus a flag
can be tested and cleared in one operation.
All the PSW bits are directly addressable, so the Parity bit, or the general purpose flags,
for example, are also available to the bit-test instructions.
1.8.1 Relative Offset
The destination address for these jumps is specified to the assembler by a label or by an
actual address in Program Memory. However, the destination address assembles to a
relative offset byte. This is a signed (two’s complement) offset byte which is added to the
PC in two’s complement arithmetic if the jump is executed.
The range of the jump is therefore -128 to +127 Program Memory bytes relative to the
first byte following the instruction.

Atmel 8051 Specifications

General

Architecture	8-bit
Serial Communication	UART
CPU	8051
Program Memory	Up to 64 KB Flash
Timers/Counters	2 or 3 (16-bit)
SPI	Yes
I2C	Yes
ADC	Yes (some variants)
Operating Voltage	2.7V to 5.5V
Operating Temperature	-40°C to +85°C
Package	DIP, PLCC, TQFP

Summary

Section 1: The 8051 Instruction Set

1.1 Program Status Word

Details the Program Status Word (PSW) register, its bits, and their functions.

1.2 Addressing Modes

Describes the various addressing modes used by the 8051 instruction set.

1.3 Arithmetic Instructions

Lists and explains the arithmetic instructions available on the 8051.

1.4 Logical Instructions

Details the bitwise logical operations performed by the 8051 instruction set.

1.5 Data Transfers

Covers instructions for moving data between registers and memory.

1.6 External RAM

Details instructions for accessing external data memory.

1.7 Lookup Tables

Describes instructions for reading data from program memory tables.

1.8 Boolean Instructions

Covers the 8051's single-bit processor and its instructions.

1.9 Jump Instructions

Explains instructions that alter program flow, including jumps and calls.

1.10 Read-Modify Write Instruction Features

Explains instructions that read, modify, and write back data.

1.11 Instruction Set Summary

Provides a comprehensive list of 8051 instructions with byte and cycle counts.

1.12 Instructions That Affect Flag Settings

Lists instructions that modify the status flags in the PSW register.

1.13 Instruction Table

Presents a table of 8051 instructions with hex values and execution times.

1.14 Instruction Definitions

Provides detailed descriptions and operation of individual 8051 instructions.

Section 2: Common Features Description

2.1 Introduction

Introduces the chapter on on-chip hardware features of 8051 microcontrollers.

2.2 Special Function Registers

Details the Special Function Register (SFR) map and key registers.

2.3 Oscillator and Clock Circuit

Explains the on-chip oscillator and clock generation system.

2.4 CPU Timing

Details the CPU's fetch/execute cycles and timing characteristics.

2.5 Port Structures and Operation

Details the structure and operation of the 8051's I/O ports.

2.6 Accessing External Memory

Explains accessing external program and data memory via 8051 pins.

2.8 ALE

Explains the Address Latch Enable (ALE) signal for address multiplexing.

2.9 Timer/Counters

Introduces the two general-purpose 16-bit timers/counters in the 80C51.

2.10 Timer 0

Details the four operating modes of Timer 0.

2.11 Timer 1

Details Timer 1's operation, similar to Timer 0 but with mode 3 differences.

2.12 Timer 2

Details Timer 2 features: capture, auto-reload, and baud rate generation.

2.13 Serial Interface

Describes the Universal Asynchronous Receiver/Transmitter (UART) features.

2.14 Framing Error Detection

Explains the feature for detecting framing errors in asynchronous serial modes.

2.15 Automatic Address Recognition

Describes hardware feature for multiprocessor communication address matching.

2.16 Interrupts

Covers interrupt handling, priority levels, and response times.