Atmel 8051 User Manual

The 8051 Instruction Set
1-7 Atmel 8051 Microcontrollers Hardware Manual
4316B–8051–02/04
Note that Boolean operations can be performed on any byte in the internal Data Memory
space without going through the Accumulator. The XRL <byte>, # data instruction, for
example, offers a quick and easy way to invert port bits, as in
XRL P1, #OFFH
If the operation is in response to an interrupt, not using the Accumulator saves the time
and effort to stack it in the service routine.
The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right.
For a left rotation, the MSB rolls into the LSB position. For a right rotation, the LSB rolls
into the MSB position.
The SWAP A instruction interchanges the high and low nibbles within the Accumulator.
this is a useful operation in BCD manipulations. For example, if the Accumulator con-
tains a binary number which is known to be less than 100, it can be quickly converted to
BCD by the following code:
MOV B, #10
DIV AB
SWAP A
ADD A,B
Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and
the ones digit in the B register. The SWAP and ADD instructions move the tens digit to
the high nibble of the Accumulator, and the ones digit to the low nibble.
1.5 Data Transfers
1.5.1 Internal RAM
Table 1-4 shows the menu of instructions that are available for moving data around
within the internal memory spaces, and the addressing modes that can be used with
each one. With a 12 MHz clock and X1 mode, all of these instructions execute in either
1 or 2 µs.
The MOV <dest>, <src> instruction allows data to be transferred between any two inter-
nal RAM or SFR locations without going through the Accumulator. Remember the Upper
128 bytes of data RAM can be accessed only by indirect, and SFR space only by direct
addressing.
Note that in all 8051 devices, the stack resides in on-chip RAM, and grows upwards.
The PUSH instruction first increments the Stack Pointer (SP), then copies the byte into
the stack. PUSH and POP use only direct addressing to identify the byte being saved or
restored, but the stack itself is accessed by indirect addressing using the SP register.

Atmel 8051 Specifications

General

Architecture	8-bit
Serial Communication	UART
CPU	8051
Program Memory	Up to 64 KB Flash
Timers/Counters	2 or 3 (16-bit)
SPI	Yes
I2C	Yes
ADC	Yes (some variants)
Operating Voltage	2.7V to 5.5V
Operating Temperature	-40°C to +85°C
Package	DIP, PLCC, TQFP

Summary

Section 1: The 8051 Instruction Set

1.1 Program Status Word

Details the Program Status Word (PSW) register, its bits, and their functions.

1.2 Addressing Modes

Describes the various addressing modes used by the 8051 instruction set.

1.3 Arithmetic Instructions

Lists and explains the arithmetic instructions available on the 8051.

1.4 Logical Instructions

Details the bitwise logical operations performed by the 8051 instruction set.

1.5 Data Transfers

Covers instructions for moving data between registers and memory.

1.6 External RAM

Details instructions for accessing external data memory.

1.7 Lookup Tables

Describes instructions for reading data from program memory tables.

1.8 Boolean Instructions

Covers the 8051's single-bit processor and its instructions.

1.9 Jump Instructions

Explains instructions that alter program flow, including jumps and calls.

1.10 Read-Modify Write Instruction Features

Explains instructions that read, modify, and write back data.

1.11 Instruction Set Summary

Provides a comprehensive list of 8051 instructions with byte and cycle counts.

1.12 Instructions That Affect Flag Settings

Lists instructions that modify the status flags in the PSW register.

1.13 Instruction Table

Presents a table of 8051 instructions with hex values and execution times.

1.14 Instruction Definitions

Provides detailed descriptions and operation of individual 8051 instructions.

Section 2: Common Features Description

2.1 Introduction

Introduces the chapter on on-chip hardware features of 8051 microcontrollers.

2.2 Special Function Registers

Details the Special Function Register (SFR) map and key registers.

2.3 Oscillator and Clock Circuit

Explains the on-chip oscillator and clock generation system.

2.4 CPU Timing

Details the CPU's fetch/execute cycles and timing characteristics.

2.5 Port Structures and Operation

Details the structure and operation of the 8051's I/O ports.

2.6 Accessing External Memory

Explains accessing external program and data memory via 8051 pins.

2.8 ALE

Explains the Address Latch Enable (ALE) signal for address multiplexing.

2.9 Timer/Counters

Introduces the two general-purpose 16-bit timers/counters in the 80C51.

2.10 Timer 0

Details the four operating modes of Timer 0.

2.11 Timer 1

Details Timer 1's operation, similar to Timer 0 but with mode 3 differences.

2.12 Timer 2

Details Timer 2 features: capture, auto-reload, and baud rate generation.

2.13 Serial Interface

Describes the Universal Asynchronous Receiver/Transmitter (UART) features.

2.14 Framing Error Detection

Explains the feature for detecting framing errors in asynchronous serial modes.

2.15 Automatic Address Recognition

Describes hardware feature for multiprocessor communication address matching.

2.16 Interrupts

Covers interrupt handling, priority levels, and response times.