Atmel ATtiny85 User Manual

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7598H–AVR–07/09
ATtiny25/45/85
12.8.5 Output Compare Register B – OCR0B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
12.8.6 Timer/Counter Interrupt Mask Register – TIMSK
• Bits 7..4, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
12.8.7 Timer/Counter 0 Interrupt Flag Register – TIFR
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
Bit 76543210
OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543 210
–
OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK
Read/Write R R R R R/W R/W R/W R
Initial Value 00000 000
Bit 76543210
–
OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 –TIFR
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0

Atmel ATtiny85 Specifications

General

Architecture	8-bit AVR
Flash Memory	8 KB
SRAM	512 B
EEPROM	512 B
Clock Speed	20 MHz
GPIO Pins	6
ADC Channels	4
ADC Resolution	10-bit
Timers	2 (8-bit)
PWM Channels	2
Operating Voltage	2.7V - 5.5V
Communication Interfaces	SPI, I2C
Package	DIP-8, SOIC-8
Operating Temperature	-40°C to 85°C

Summary

ATtiny25/45/85 Features Overview

High-Performance AVR Microcontroller

Details on the advanced RISC architecture and its benefits for performance.

Non-volatile Program and Data Memories

Information on Flash, EEPROM, and SRAM capacities and endurance.

Peripheral Features

Overview of integrated peripherals like Timers, ADC, and USI.

Low Power Consumption

ATtiny25/45/85 Pin Configuration

ATtiny25/45/85 Block Diagram

ATtiny25/45/85 Pin Descriptions

AVR CPU Core

Architectural Overview

Explanation of the Harvard architecture and pipelining.

General Purpose Register File

Reset and Interrupt Handling

Explanation of reset sources and interrupt vector handling.

AVR ATtiny25/45/85 Memories

In-System Re-programmable Flash Program Memory

Details on Flash memory size, endurance, and programming.

SRAM Data Memory Organization

Description of SRAM organization and addressing modes.

EEPROM Data Memory

Information on EEPROM capacity, endurance, and access.

System Clock and Clock Options

Clock Sources

System Clock Prescaler

Explanation of the Clock Prescale Register (CLKPR) for clock frequency control.

Power Management and Sleep Modes

MCU Control Register (MCUCR)

Power-down Mode Operation

Minimizing Power Consumption

Strategies for reducing power consumption in the device.

System Control and Reset

Reset Sources

Overview of the four reset sources: Power-on, External, Watchdog, Brown-out.

Power-on Reset (POR)

Details on the POR circuit, detection level, and start-up timing.

External Reset

Brown-out Detection (BOD)

Information on the on-chip BOD circuit and selectable trigger levels.

Watchdog Timer

Details on the Watchdog Timer operation, configuration, and reset.

Interrupts

Interrupt Vectors in ATtiny25/45/85

I/O Ports

Ports as General Digital I/O

External Interrupts

8-bit Timer/Counter0 with PWM

Overview of Timer/Counter0

Modes of Operation

Explanation of Normal, CTC, Fast PWM, and Phase Correct PWM modes.

8-bit Timer/Counter Register Description

Counter and Compare Units

Timer/Counter1 Overview

Timer/Counter1 in PWM Mode

Details on generating PWM waveforms with Timer/Counter1.

Universal Serial Interface (USI)

Overview of USI

Two-wire Mode Operation

Analog Comparator

Analog Comparator Control and Status Register (ACSR)

Analog to Digital Converter (ADC)

ADC Features

Overview of ADC resolution, conversion time, and input channels.

ADC Operation

Explanation of the ADC conversion process and voltage references.

Starting a Conversion

Methods for initiating ADC conversions, including auto-triggering.

ADC Conversion Result

Details on how the conversion result is presented and interpreted.

ADC Multiplexer Selection Register (ADMUX)

ADC Control and Status Register A (ADCSRA)

debugWIRE On-chip Debug System

debugWIRE Features

Self-Programming the Flash

Performing Page Erase by SPM

Filling the Temporary Buffer (Page Loading)

Memory Programming

Fuse Bytes Overview

Serial Downloading

High-voltage Serial Programming

Procedures for programming Flash, EEPROM, Lock bits, and Fuses.

Electrical Characteristics

Absolute Maximum Ratings

DC Characteristics

Typical Characteristics