BCI Capnocheck Plus - Speaker Volume Controller

Chapter 3: Capnocheck Plus Circuit Description
The timing diagrams of the Display Write and Read Cycles are shown on the
schematic. From the microprocessor’s “point of view”, the Display Board
represents a general purpose I/O device, controlled using signals /CS - select,
[WR - write, /RD - read and A0 - Command/Data select. Signals /DCS and
DIR control the bi-directional buffer and prevent any possible bus conflicts
between Display Board, buffer and microprocessor.
Speaker Volume Controller.
Speaker Volume Controller is located in FPGA U4. The corresponding
fragment of FPGA is shown on the following drawing:
4. 608nH2
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1,152HHz
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code Lag RESET UCS
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The volume control code is stored by the microprocessor into a four bit parallel
register. Code 0 corresponds to the lowest volume, code F - to the highest.
Volume control circuitry inside FPGA also includes a binary counter which
divides the microprocessor clock frequency. The by-products of this counter
are the clock frequency for the Analog - to - Digital Converter (signal
ADCCLK) and for the DC-DC converter (signal PSCLK). The binary code
from the divider is compared with the number stored in the four bit parallel
register. The result of the comparison is the pulse train with a variable duty
cycle which depends on the number stored in the parallel register. If the
number equals zero, the duty factor is 1/16, if the number equals F, the duty
factor is 1, or the output represents constant logical “one”. Then the signal is
gated with the TONE signal - audio frequency signal generated by the
microprocessor. The external R-C filter converts the resulting pulse train into
an audio frequency signal, the amplitude of which is directly proportional to
the number stored in the parallel register. Hence, a total of 16 levels of volume,
plus OFF, can be achieved with this circuitry.
Capnocheck Plus Service Manual 3-5