BCI Capnocheck Plus - Microprocessor and Address Decoding

Chapter 3: Capnocheck Plus Circuit Description
There are several conditions which can power down the Monitor. If the
STNBY/ON key is pressed, the microprocessor generates a /HALT signal
which pulls down the PFI input of the voltage comparator inside U19. The
output open drain signal, /PFO, goes low and turns off U20 by pulling EN low.
The other condition for turning the Monitor off is a low battery. The battery
voltage is measured by the resistor divider R65-R65. If this voltage is lower
than the 1.25VDC threshold of the internal comparator U19, the output signal,
/PFO, goes low.
In addition, the output of the resistor divider is connected to the Analog-to-
Digital converter, and is read by the microprocessor to give an early warning
about low battery condition.
Microprocessor Section and Address Decoders
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Microprocessor U1 is a Zilog Z180. Its address and data buses are connected to
the One Time Programmable Read Only Memory (OTP ROM) U2 and
Random Access Memory (RAM) U3. A Memory Address Decoder is
implemented in the Field Programmable Gate Array (FPGA) U4. The
following
drawing shows the Memory Address Decoder section of FPGA:
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The memory address map is shown in the following table:
Device Address Space
OTP ROM 0..1FFFF
RAM 20000 .. 23FFF
FPGA U4 also includes a RAM Page Selector used to split the whole RAM
area into pages, which can be accessed by the microprocessor. The
corresponding section of FPGA is shown on the following drawing:
3-2
Capnocheck Plus Service Manual