Clevo D900K - Power Controller 1; Power Controller 2

Schematic Diagrams
POWER CONTROLLER 1 B - 31
B.Schematic Diagrams
POWER CONTROLLER 1
S1 ON S3 OFF
VDDA_EN High: Enable Low :disable
R649
47K
9
10
8
14
7
U21C
74HC08
3 4
14
7
U26B
74LVC14
C326
0.1U
1
2
3
14
7
U21A
74HC08
T
R650
47K
IN
1
IN
2
GND
3
VCC
5
OUT
4
U15
TC7S32F
R666 0
B
E
C
Q16
2N3904
R667 0
T
R668 0(R)
R647
4.7K
CE
B
Q3
DTC114EUA
IN
1
IN
2
GND
3
VCC
5
OUT
4
U29
74AHC1G08
T
2
1
4
3
5
U16
TC7SZ08
B
E
C
Q17
2N3904
C906
0.47U
R222
47K
R669 10K
R25
15K
C284
0.1U(R)
4
5
6
14
7
U21B
74HC08
C286
0.1U
AC
D36 1N4148
1 2
14
7
U26A
74LVC14
12
13
11
14
7
U21D
74HC08
C305
0.1U
R648 1M
C907
0.1U
IN
1
IN
2
GND
3
VCC
5
OUT
4
U23
TC7S32F
C285
0.1U
C912
0.1U(R)
R211
4.7K
B
E C
Q13
2N3904
C908
0.22U(R)
VDD3
VDD3
VDD3VDD3
VDD3
VDD3
+1.2VLDT
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
+2.5VDDA
+1.2VLDT
VDD3 (3,11,12,14,16,18,21,24,26,31,32,33,34,35)
VDD5 (13,14,16,18,23,24,26,27,32)
+2.5VDDA
DUAL_PG(31,34)
PS_ON(24)
SUSBG(31)
+12V (14,18,25,26,28,32,34)
+1.2VLDT_PG(31)
EN_VCORE (33)
+1.2VLDT_PG(31)
SUSBG(31)
VCORE_PWRGD(31,33)
1.2VLDT_PG(33)
SUSBG(31)
EN_2.5VDDA(33)
EN_+1.2VLDT(33)
+1.2VLDT(3,8,33)
SUSB# (14,17,21,24,32)
DUAL_PG(31,34)
+2.5VDDA(3,33)
2.5VDDA_PG (31)
D04
Z3533
EN_2.5VDDA
ENABLE VCORE POWER
1.2VLDT_PG
VCORE_PWRGD
SUSBG
RUN_MODE
Z3528
2.5VDDA_PG
EN_+1.2VLDT
SUSBG
2.5VDDA_PGD
Z3711 Z3722 2.5VDDA_PGD2.5VDDA_PG
Z3724
SUSB#
RUN_MODE
VCORE_PWRGD
Sheet 30 of 40
POWER
CONTROLLER 1