Clevo NL51CU - Processor 11;12

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Comet Lake U Q/20 CFG
CFG[0]: Stall reset sequence after PCU PLL
Ʉ
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Ʉ
CFG[2]: PCI Express* Static x16 Lane
Ʉ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
Ʉ
CFG[4]: eDP enable:
Ʉ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
Ʉ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
Ʉ
— 1 = (default) PEG Train immediately
following RESET# de assertion.
— 0 = PEG Wait for BIOS for training.
CFG[19:8]: Reserved configuration lanes.
Ʉ
According to CML-U DCL
611481-qs-cml-qsbf-qsbg-qsbj-dcl-ww17-2019.pdf
CFG_RCOMP
CFG0
CFG4
CFG6
CFG5
CFG7
CFG3
SKTOCC#
CFG0
1.05VA
3.3VA
VCCIO
VCCIO2,11,37
3.3VA5,6,7,8,9,12,22,23,30,33
1.05VA12,32
Title
Size Document Number R e v
Date: Sheet
of
6-71-NL4C0-D02
D02
[04] CML U D,Q/20 CFG
A3
444Friday, August 16, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NL40CU
Title
Size Document Number R e v
Date: Sheet
of
6-71-NL4C0-D02
D02
[04] CML U D,Q/20 CFG
A3
444Friday, August 16, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NL40CU
Title
Size Document Number R e v
Date: Sheet
of
6-71-NL4C0-D02
D02
[04] CML U D,Q/20 CFG
A3
444Friday, August 16, 2019
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NL40CU
R357*1K_04
R361*1K_04
R48
*150_04
R43*1K_04
T63
20 of 20
U1Q
CML_U_IP_CCG
ITP_PMODE
W4
CFG_4
J4
RSVD_15
AN3
CFG_5
M4
RSVD_12
W3
VSS_1
BP36
CFG_19
N4
CFG_6
J3
RSVD_23
H3
RSVD_13
AM4
CFG_18
N3
CFG_7
M3
RSVD_22
H4
RSVD_10
AL4
CFG_17
L4
CFG_0
T4
RSVD_21
CG1
RSVD_11
AL3
CFG_16
L3
CFG_1
R4
RSVD_20
CG2
RSVD_3
AN1
CFG_15
L1
CFG_2
T3
RSVD_27
CP3
CFG_RCOMP
AB5
RSVD_2
CR35
RSVD_30
AT3
CFG_14
J1
CFG_3
R3
RSVD_26
CR4
TP_4
BR18
RSVD_1
AU3
RSVD_31
BK36
CFG_13
L2
RSVD_25
BV25
CFG_12
J2
RSVD_24
BV24
RSVD_7
AM3
RSVD_TP_1
F37
SKTOCC#
E1
CFG_11
N1
RSVD_TP_2
F34
RSVD_6
BJ34
RSVD_TP_3
CN36
IST_TRIG
CP36
CFG_10
R1
RSVD_18
BP8
RSVD_5
BJ36
RSVD_29
BK35
CFG_8
R2
RSVD_19
BP9
TP_1
BP35
RSVD_4
AN2
CFG_9
N2
RSVD_28
CR3
TP_2
BP34
RSVD_16
BT9
TP_3
BK34
RSVD_17
BT8
RSVD_9
AL1
RSVD_14
AN4
RSVD_8
AL2
R366 1.5K_04
R3581K_04
R44 49.9_1%_04
T51
T50
R356 10K_04
Sheet 4 of 43
Processor 3/12
Schematic Diagrams
Processor 3/12 B - 5
B.Schematic Diagrams
Processor 3/12