Clevo W251HPQ - Processor 7;7- RSVD

Schematic Diagrams
Processor 7/7- RSVD B - 9
B.Schematic Diagrams
Processor 7/7- RSVD
CFG2
H_C P U_R SVD2
H_C P U_R SVD1
H_C P U_R SVD4
H_C P U_R SVD3
On CR B
H_SNB _IVB#_PWRC TRL = low , 1.0V
H_SNB _IVB#_PWRC TRL = hig h/NC, 1.05 V
CFG7
PE G DEFER TR AINI NG
1: (Default ) PEG Trai n immediat ely following xxRES ETB d e asserti on
0: PEG Wait for BIOS for traini ng
CFG5
CFG6
CFG4
CFG2
PE G Static L ane Rever sal - CFG2 is f or the 16 x
1: (Defa ult) Norm al Op eration; L ane #
de finit ion match es so cket pin m ap d efini tion
0: Lane Reversed
CFG2
Sandy Bridge Processor 7/7 ( RESERVED )
CFG4
CFG7
RESERVED
U29E
PZ 98827-364B- 01F
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL 2 6
CFG[3]
AL 2 7
CFG[4]
AK26
CFG[5]
AL 2 9
CFG[6]
AL 3 0
CFG[7]
AM3 1
CFG[8]
AM3 2
CFG[9]
AM3 0
CFG[10]
AM2 8
CFG[11]
AM2 6
CFG[12]
AN2 8
CFG[13]
AN3 1
CFG[14]
AN2 6
CFG[15]
AM2 7
CFG[16]
AK31
CFG[17]
AN2 9
RSVD34
AM3 3
RSVD35
AJ 2 7
RSVD38
J16
RSVD42
AT3 4
RSVD39
H16
RSVD40
G16
RSVD41
AR 3 5
RSVD43
AT3 3
RSVD45
AR 3 4
RSVD56
AT2
RSVD57
AT1
RSVD58
AR 1
RSVD46
B3 4
RSVD47
A3 3
RSVD48
A3 4
RSVD49
B3 5
RSVD50
C35
RSVD51
AJ 3 2
RSVD52
AK 32
RSVD30
AE 7
RSVD31
AK 2
RSVD28
L7
RSVD29
AG 7
RSV D27
J15
RSV D16
C30
RSV D15
D23
RSV D17
A31
RSV D18
B30
RSV D20
D30
RSV D19
B29
RSV D22
A30
RSV D21
B31
RSV D23
C29
RSV D24
J20
RSVD37
T8
RSV D6
B4
RSV D7
D1
RSV D8
F25
RSV D9
F24
RSV D11
D24
RSV D12
G25
RSV D13
G24
RSV D14
E23
RSVD32
W8
RSVD33
AT2 6
RSV D25
B18
RSVD44
AP 35
RSV D10
F23
RSV D5
AJ2 6
VA XG_ VAL _ S EN SE
AJ3 1
VS SA XG_VAL_S ENSE
AH3 1
VCC _ VA L _ SE NSE
AJ3 3
VS S_V AL_ SE NSE
AH3 3
KEY
B1
VCC_DIE_SENSE
AH 2 7
VCC I O_SE L
A19
RSVD54
AN 3 5
RSVD55
AM3 5
R111 * 1K_04
R429 10K_1%_04
R430 *10m il _short _04
R417 * 1K_04
R109 * 1K_04
R114 * 1K_04
R107 * 1K_04
Q12
*MTN2306AN3
G
D S
Q11
*MTN2306AN3
G
D S
DRAMRST_CNTRL3, 19
VR EF _ CH_A_DIMM
H_SNB_IVB#_PWRCTR L
VR EF _ CH_B_DIMM
H_S N B_IV B#_PW RC TRL_R
CFG7
CFG Straps for Processor
3.3V2,3,11, 16,18, 19,20,22, 23,24,25, 27, 28,29, 30,35,37, 38,39
CFG5
Di splay Port Pre sence Strap
1: (Defa ult) Disa bled; No Physic al D ispla y Por t
at tache d to Embe dded Display Po rt
0: Enabl ed; An ex terna l Display Port devi ce is
co nnect ed t o the Embe dded Displ ay P ort
CFG4
VRE F_ D Q_ CHB10
VRE F_ D Q_ CHA9
CFG0
R129
*1K _04
R136
*1K_04
CFG6
R138 *0_04
R134 *0_04
PC IE Port Bi furc ation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG[6:5]
3.3V
Sheet 8 of 49
Processor 7/7-
RSVD