5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AMI Debug Use
Internal PD 20K CMOS
Internal PD 20K CMOS
GPIO_81,193
Ensure that this strap is pulled HIGH when
RSM_RST_N de-asserts for normal platform operation.
Internal PU 20K CMOS
LPC 1.8V/3.3V mode select
1=buffers set to 1.8V mode
0=buffers set to 3.3V mode (default)
Internal PD 20K CMOS
Internal PU 20K CMOS
Allow SPI as a boot source
1=disable
0=enable (default)
Internal PD 20K CMOS
Internal PD 20K CMOS
Internal PD 20K CMOS
Internal PD 20K CMOS
Internal PD 20K CMOS
eSPI Flash Sharing Mode
1=slave attached flash sharing (SAFS);
0=master attached flash sharing (MAFS;default)
Internal PD 20K CMOS
Internal PU 20K CMOS
Internal PD 20K CMOS
Internal PD 20K CMOS
Internal PD 20K CMOS
GPIO_62,79,80,85,86,87,89,192,194,196
Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation.
Enable TXE ROM Bypass
1=enable bypass
0=disable bypass (default)
Hardware Straps (4)
Internal PD 20K CMOS
PLACE CLOSE TO SOC
Force DNX FW Load
1=Force
0=Do not force (default)
Internal PD 20K CMOS
LPC boot BIOS strap
1=boot from LPC
0=do not boot from LPC (default)
Internal PD 20K CMOS
6-07-3R374-1A0
D02 CNVI
㕘⡆
CLOSE TO PCH
D02 CLOSE TO CONN
D02
⇒昌枸䔁
D02
⇒昌枸䔁
D02
⇒昌枸䔁
D02
⇒昌枸䔁
UART1_RXD_Q
UART1_TXD_Q
SOC_GPIO79
SOC_GPIO80
SOC_GPIO81
SOC_GPIO83
SOC_GPIO84
SOC_GPIO85
SOC_GPIO86
SOC_GPIO87
SOC_GPIO89
SOC_GPIO191
SOC_GPIO192
SOC_GPIO193
SOC_GPIO194
SOC_GPIO196
SOC_GPIO62 UART0_TXD
SOC_CLKIN_XTAL_LCP
UART2_TXD
SOC_GPIO66
CNVI_WT_RCOMP
SOC_GPIO191
SOC_GPIO194
SOC_GPIO193
SOC_GPIO192
SOC_GPIO196
SOC_CLKIN_XTAL_LCP
SMB_ALERT#
SOC_GPIO79
SOC_GPIO80
SOC_GPIO81
SOC_GPIO83
SOC_GPIO84
SOC_GPIO85
SOC_GPIO86
SOC_GPIO87
SOC_GPIO89
UART0_RXD
UART2_RXD
UART0_TXD
SOC_GPIO62
UART2_TXD
SOC_GPIO66
UART2_RXD
UART2_TXD
UART0_TXD
UART0_RXD
SOC_GPIO193
1.8VA 1.8VA
3.3VA
3.3VA
1.8VA
1.8VA
SMB_CLK[11]
XTAL_CLKREQ[18]
CNVI_RGI_RSP[18]
CNVI_RGI_DT[18]
CNVI_BRI_RSP[18]
CNVI_BRI_DT[18]
CNVI_RF_RST#[18]
SMB_DATA[11]
CNVI_WGR_CLK_DP[18]
CNVI_WGR_CLK_DN[18]
CNVI_WT_D0P[18]
CNVI_WGR_D0P[18]
CNVI_WGR_D1P[18]
CNVI_WGR_D0N[18]
CNVI_WT_D0N[18]
CNVI_WGR_D1N[18]
CNVI_WT_D1N[18]
CNVI_WT_D1P[18]
CNVI_WT_CLK_DP[18]
CNVI_WT_CLK_DN[18]
CLKIN_XTAL_LCP[18]
3.3VA[7,8,9,19,22,23,24,26]
1.8VA[3,4,5,7,8,9,11,17,18,19,22,23,24]
Title
Size Document Number Rev
Date: Sheet
of
6-71-W51G0-D02
3.0
[06] SMB/CNV
A3
635Tuesday, January 30, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-W51G0-D02
3.0
[06] SMB/CNV
A3
635Tuesday, January 30, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-W51G0-D02
3.0
[06] SMB/CNV
A3
635Tuesday, January 30, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
S
D
G
Q15B
*MTDK3S6R
5
34
R380 33_04
S
D
G
Q15A
*MTDK3S6R
2
61
LPSS_I2C
LPSS_UART
LPSS_SPI
LPSS SMBus
CNVI
6 OF 13
U25F
CNV_WT_RCOMP
F33
XTAL_CLKREQ
F19
CLKIN_XTAL_LCP
J29
SIO_I2C4_SDA
R51
SIO_UART0_TXD
N54
SIO_UART2_RXD
M53
SIO_SPI_2_CLK
M37
CNV_WGR_CLK
H31
CNV_RGI_DT
D19
SIO_SPI_0_FS0
L37
SIO_UART2_RTS
K53
SMB_CLK
B27
SIO_I2C5_SDA
A50
SIO_UART2_TXD
L54
SIO_SPI_0_FS1
J39
CNV_RGI_RSP
D17
SIO_I2C6_SDA
C47
SIO_SPI_2_FS0
P33
SIO_I2C7_SDA
C46
SIO_SPI_2_FS1
P37
CNV_WGR_D0_P
M31
SMB_DATA
C27
SIO_SPI_2_FS2
L35
CNV_WGR_D1_P
D29
SIO_UART0_CTS
M55
CNV_WT_D1
J31
CNV_WGR_D1
F29
CNV_WGR_D0
P31
CNV_WT_D0
H35
SIO_I2C0_SCL
U49
SIO_UART0_RTS
N53
CNV_WT_CLK_P
F35
CNV_WT_CLK
D35
SMB_ALERT
A26
SIO_I2C1_SCL
U46
CNV_BRI_DT
H17
SIO_I2C2_SCL
AA39
SIO_I2C3_SCL
R44
SIO_SPI_0_RXD
L39
CNV_RF_RESET
F17
SIO_I2C4_SCL
R49
SIO_I2C0_SDA
U51
SIO_SPI_2_RXD
P35
SIO_SPI_0_TXD
J37
CNV_WT_D0_P
J35
SIO_I2C5_SCL
C50
SIO_I2C1_SDA
U48
CNV_WT_D1_P
L31
CNV_BRI_RSP
J17
SIO_I2C6_SCL
C48
SIO_UART0_RXD
P53
SIO_SPI_0_CLK
M39
SIO_SPI_2_TXD
M33
CNV_WGR_CLK_P
H29
SIO_I2C7_SCL
B47
SIO_I2C2_SDA
AA41
SIO_I2C3_SDA
R43
SIO_UART2_CTS
L53
R388
FCM1005KF-121T03
R154
*2.2K_04
R106 10K_04
R102 0_04
R168
*2.2K_04
R158 *0_04
R385
10K_04
C332
3.3p_50V_NPO_04
R383 33_04
R368 *1K_04
R3781K_04
R381 33_04
R120 4.7K_1%_04
R3761K_04
R387 33_04
R178 *0_04
R129 150_1%_04
R446 20K_04
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