EasyManua.ls Logo

Clevo W670RCW - Processor 3;6

Clevo W670RCW
112 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG7
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
CFG[0]: Stall reset sequence after PCU
Ʉ
ɄɄ
Ʉ
PLL lock until de-asserted:
— 1 = (Default) Normal Operation;
No stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Ʉ
ɄɄ
Ʉ
CFG[2]: PCI Express* Static x16 Lane
Ʉ
ɄɄ
Ʉ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
Ʉ
ɄɄ
Ʉ
CFG[4]: eDP enable:
Ʉ
ɄɄ
Ʉ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
Ʉ
ɄɄ
Ʉ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
Ʉ
ɄɄ
Ʉ
— 1 = (default) PEG Train
immediately following RESET# de
assertion.
— 0 = PEG Wait for BIOS for
training.
CFG[19:8]: Reserved configuration
Ʉ
ɄɄ
Ʉ
lanes.
TO EC
NEAR CPU
TO PCH-H
VCCST_PWRGD
CAD Note: Capacitor need to be placed
close to buffer output pin
VIDALERT#
PROCHOT#
H_PROCHOT#
VCCST_PWRGD_CPUVCCST_PWRGD
PM_DOWN
PECI
H_SKTOCC_N
PROC_SELECT#
H_CATERR#
SKL_XDP_MBP_0
SKL_XDP_MBP_1
SKL_MBP_2
SKL_MBP_3
H_TDO
H_TDI
H_TMS
H_TCK
H_TRST#
H_PREQ#
H_PRDY#
CFG_RCOMP
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
H_TDO
H_TCK
H_SKTOCC_N
CFG9
SYS_PWRGD#
VCCST_PWRGD
H_PROCHOT#
1.0V_VCCST
3.3VA
1.0V_VCCST
1.0V_VCCST
VDD3
1.0DX_VCCSTG
1.0DX_VCCSTG [6,47,50]
VDD3 [22,23,25,28,30,32,34,36,37,38,40,41,42,43,47,50]
VCCIO [2,6,42]
1.0V_VCCST [6,24,25,42,46,48]
H_PROCHOT#[46,48,50]
PCH_CPU_BCLK_R_DN[27]
PCH_CPU_BCLK_R_DP[27]
PCH_CPU_PCIBCLK_R_DN[27]
PCH_CPU_PCIBCLK_R_DP[27]
CPU_24MHZ_R_DN[27]
CPU_24MHZ_R_DP[27]
H_PWRGD[25]
PLTRST_CPU_N[24]
H_PM_SYNC[24]
H_SKTOCC_N[26]
DDR_VTT_PG_CTRL[44]
H_CPU_SVIDCLK[46,48]
H_CPU_SVIDDAT[46,48]
H_CPU_SVIDALRT#[46,48]
PCH_THERMTRIP#[24]
PCH_PECI[24]
H_PM_DOWN[24]
H_PECI[40]
3.3VA [9,22,23,24,25,28,30,47]
ALL_SYS_PWRGD[19,23,40,46,48]
H_PROCHOT_EC[40]
Title
Size Document Number Rev
Date: Sheet
of
6-71-W65R0-DN3
D03
[04]Processor 4/7-CLK/JTAG/MISC
A3
459Tuesday, May 10, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-W65R0-DN3
D03
[04]Processor 4/7-CLK/JTAG/MISC
A3
459Tuesday, May 10, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-W65R0-DN3
D03
[04]Processor 4/7-CLK/JTAG/MISC
A3
459Tuesday, May 10, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R445 *12.1_1%_04
R444 499_1%_04
R460
56.2_1%_04
R24 1K_04
T229
C9
47P_50V_NPO_04
SKYLAKE_HALO
BGA1440
5 OF 14
REV = 1
?
?
U29E
QHPW
PROC_SELECT#
BN1
CATERR#
BM30
SKTOCC#
BR33
PM_DOWN
BP31
PM_SYNC
BM34
RESET#
BP35
PROCPWRGD
BT31
VCCST_PWRGD
H13
CFG[17]
BN23
CFG[15]
BT19
CFG[16]
BP23
CFG[11]
BT22
CFG[12]
BM19
CFG[10]
BT23
CFG[9]
BR22
CLK24N
D31
CFG[1]
BN27
CFG[3]
BN28
CFG[18]
BN22
PROC_TDI
BL32
CFG[0]
BN25
CFG[2]
BN26
CFG[4]
BR20
CFG[6]
BT20
CFG[5]
BM20
CFG[7]
BP20
CFG[8]
BR23
CFG[13]
BR19
CFG[14]
BP19
CFG[19]
BP22
PROC_PREQ#
BL30
PROC_PRDY#
BP27
VIDSCK
BH32
PROC_TDO
BT28
CLK24P
E31
PCI_BCLKN
C36
PCI_BCLKP
D35
BCLKN
A32
VIDSOUT
BH29
PROCHOT#
BR30
DDR_VTT_CNTL
BT13
CFG_RCOMP
BT25
PROC_TRST#
BP30
PROC_TCK
BR28
PROC_TMS
BP28
VIDALERT#
BH31
THERMTRIP#
J31
PECI
BT34
BCLKP
B31
BPM#[0]
BR27
BPM#[1]
BT27
BPM#[2]
BM31
BPM#[3]
BT30
S
D
G
Q23B
MTDK3S6R
5
34
R28
100K_04
T120
C904
*0.1u_10V_X7R_04
R416
1K_04
R81 1K_04
R65 60.4_1%_04
R440 *0402_short
T123
C633
*0.1u_10V_X7R_04
R458
220_04
S
D
G
Q23A
MTDK3S6R
2
61
R700 20K_04
R452 1K_04
T226
R449 20_1%_04
Q3
2SK3018S3
G
DS
R447 51_04
R438
49.9_1%_04
T227
R422
100K_04
R443 51_04
R459
100_04
T228
R450 100K_04
R451 1K_04
Sheet 4 of 59
Processor 3/6
Schematic Diagrams
Processor 3/6 B - 5
B.Schematic Diagrams
Processor 3/6

Table of Contents

Related product manuals