Crown MARCO-TECH 5000VZ - ODEP Control Signal Integration; ODEP Control Tapping Points

Notes
AIso tapping in to the ODER output control of LS bias feed and Volíage
Translator feed are signáis from the fault, power (turn-on delay), and
power loss (brown-ouí) circuits. By using íhe output of ODER for ±LL
and ±LH control, these sources can mute the audio to the output stage:
a. untíl power-up delay has timed out; b. immediately upon ¡ndication
of any failure mode; c. and immediately upon loss of AC mains (power-
down or actual loss of AC sen/ice).
±TEMP signáis are produced by U500 and U501 on the output modules.
U108, on the main module, is a buffer which drives the temperature
sense test point. U117A has a fixed window voltage of 6.2V via Zener
D129. If heatsink temperature leve! exceeds about 130°C U117A
output will cause both the positive and negative ODER amplifiers to go
into hard ODER iimiting. When thethermal condition clearsthis limiting
condition will also clear.
+VCC enters via dual PNP transistor pack U116. Positive ODER bias
isadjustedbyR182. The voltage atthat point controls the static balance
of the U116 device. U116 combines the VCC and output current sense
information, the output of which represents output power level. The
common output is brought into RN101 where it provides the reference
for temperature and power. U112B isthe active device and, together
Positive ODER
-15V
2 U116 / H180
UPA75HA > 100
< +ICOM1
14-MA-5000VZ