Cypress CYW43353 - 12 Pinout and Signal Descriptions; Ball Maps

Document No. 002-14949 Rev. *E Page 56 of 113
PRELIMINARY
CYW43353
12. Pinout and Signal Descriptions
12.1 Ball Maps
Figure 29 shows the WLBGA ball map.
Figure 29. 145-Ball WLBGA (Top View)
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A
NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT
A
B
SR_PVSS SR_VLX WL_REG_ON LPO_IN GPIO_3 GPIO_0
HSIC_DATA HSIC_STROBE RREFHSIC
SDIO_DATA_0 SDIO_CLK SDIO_CMD
B
C
SR_VDDBATP5V SR_VDDBATA5V PMU_AVSS GPIO_6 GPIO_4 GPIO_1 WL_VDDC
HSIC_AVDD12PLL
HSIC_DVDD12 SDIO_DATA_1 SDIO_DATA_3 WL_VDDC
C
D
LDO_VDD1P5 VOUT_CLDO BT_REG_ON GPIO_7 GPIO_5 GPIO_2 VSSC
HSIC_AGNDPLL
VDDIO_SD SDIO_DATA_2 VSSC RF_SW_CTRL_4
D
E
VOUT_3P3 VOUT_LNLDO VSSC JTAG_SEL BT_UART_CTS VDDIO_RF VSSC RF_SW_CTRL_8 RF_SW_CTRL_3 RF_SW_CTRL_2
E
F
VOUT_BTLDO2P5 LDO_VDDBAT5V VDDIO RF_SW_CTRL_9 BT_UART_RTS BT_UART_TXD RF_SW_CTRL_5 RF_SW_CTRL_1 RF_SW_CTRL_0
F
G
BT_PCM_IN BT_PCM_CLK WL_VDDC WL_VDDC BT_UART_RXD RF_SW_CTRL_7 WL_VDDC BBPLL_AVS WRF_XTAL_GND1P2 BBPLL_AVDD1P2
G
H
GPIO_8 BT_PCM_SYNC CLK_REQ BT_VDDIO BT_VDDC BT_I2S_WS WRF_GPIO_OUT WRF_WL_LNLDOIN_VDD1P5 RF_SW_CTRL_6 WRF_VCO_GND WRF_XTAL_VDD1P5 WRF_XTAL_IN
H
J
BT_HOST_WAKE BT_PCM_OUT BT_VDDC VSSC BT_I2S_CLK WRF_TSSI_A WRF_BUCK_GND1P5 WRF_MMD_GND1P2 WRF_PFD_GND1P2 WRF_CP_GND WRF_XTAL_OUT
J
K
BT_DEV_WAKE VSSC BT_I2S_DI BT_I2S_DO WRF_AFE_GND1P2 WRF_LO_GND1P2_2 WRF_SYNTH_VBAT_VDD3P3 WRF_MMD_VDD1P2 WRF_PFD_VDD1P2 WRF_XTAL_VDD1P2
K
L
BT_IFVDD1P2 BT_PLLVSS BT_IFVSS WRF_RX2G_GND1P2 WRF_TX_GND1P2 WRF_PADRV_VBAT_VDD3P3 WRF_PADRV_VBAT_GND3P3 WRF_LO_GND1P2_2 WRF_RX5G_GND1P2
L
M
BT_VCOVSS BT_PLLVDD1P2 BT_PAVSS BT_AGPIO WRF_LNA_2G_GND1P2 WRF_PA_VBAT_GND3P3_4 WRF_PA_VBAT_GND3P3_3 WRF_PA_VBAT_GND3P3_2 WRF_PA_VBAT_GND3P3_1 WRF_LNA_5G_GND1P2
M
N
BT_VCOVDD1P2 BT_LNAVDD1P2 BT_RF BT_PAVDD2P5 WRF_RFIN_2G WRF_RFOUT_2G WRF_PA2G_VBAT_VDD3P3 WRF_PA5G_VBAT_VDD3P3 WRF_RFOUT_5G WRF_RFIN_5G
N
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NCF
NCF
NCF
LNF_VDD1P2
LNF_VDD1P2
LNF_VDD1P2
VSSF
VSSF
VSSF VSSF