Cypress CYW43353 - SDIO Bus Timing Specifications in SDR Modes

Document No. 002-14949 Rev. *E Page 97 of 113
PRELIMINARY
CYW43353
18.1.3 SDIO Bus Timing Specifications in SDR Modes
18.1.3.1. Clock Timing
Figure 34. SDIO Clock Timing (SDR Modes)
Table 46. SDIO Bus Clock Timing Parameters (SDR Modes)
Parameter Symbol Minimum Maximum Unit Comments
–t
CLK
40 – ns SDR12 mode
20 – ns SDR25 mode
10 – ns SDR50 mode
4.8 – ns SDR104 mode
–t
CR
, t
CF
– 0.2 × t
CLK
ns t
CR
, t
CF
< 2.00 ns (max.) @100 MHz, C
CARD
= 10 pF
t
CR
, t
CF
< 0.96 ns (max.) @208 MHz, C
CARD
= 10 pF
Clock duty cycle – 30 70 % –
t
CLK
t
CR
SDIO_CLK
t
CF
t
CR