Cypress CYW43353 - Lnldo

Document No. 002-14949 Rev. *E Page 91 of 113
PRELIMINARY
CYW43353
16.5 LNLDO
Table 41. LNLDO Specifications
Specification Notes Min. Typ. Max. Units
Input supply voltage, Vin Min. = 1.2V
o
+ 0.15V = 1.35V dropout voltage requirement
must be met under maximum load.
1.3 1.35 1.5 V
Output current – 0.1 – 150 mA
Output voltage, V
o
Programmable in 25 mV steps. Default = 1.2V 1.1 1.2 1.275 V
Dropout voltage At maximum load – – 150 mV
Output voltage DC accuracy Includes line/load regulation –4 – +4 %
Quiescent current No load – 44 – µA
Max. load – 970 990 µA
Line regulation V
in
from (V
o
+ 0.1V) to 1.5V, max load – – 5 mV/V
Load regulation Load from 1 mA to 150 mA – 0.02 0.05 mV/mA
Leakage current Power-down – – 10 µA
Output noise @30 kHz, 60–150 mA load C
o
= 2.2 µF
@100 kHz, 60–150 mA load C
o
= 2.2 µF
– – 60
35
nV/rt Hz
nV/rt Hz
PSRR @ 1kHz, Input > 1.35V, C
o
= 2.2 µF, V
o
= 1.2V 20 – – dB
LDO turn-on time LDO turn-on time when rest of chip is up – 140 180 µs
External output capacitor, C
o
Total ESR (trace/capacitor): 5 m–240 m
0.5
1
1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
2.2 4.7 µF
External input capacitor Only use an external input capacitor at the VDD_LDO pin
if it is not supplied from CBUCK output.
Total ESR (trace/capacitor): 30 m–200 m
– 1 2.2 µF