Cypress CYW43353 - Page 7

Document No. 002-14949 Rev. *E Page 7 of 113
PRELIMINARY
CYW43353
Figure 1. CYW43353 Block Diagram
Bluetooth
WLAN
UART
I2S
PCM
Port Control
Registers
DMA
JTAG
Master
GPIO
Timers
WD
Pause
AHB2APB
AHB Bus Matrix
RAM
ROM
ARMCM3
WLAN
Master
Slave
RX/TX
BLE
LCU
APU
BlueRF
PMU
CLB
FEM or
SP3T
FEM or
SPDT
Diplexer
Modem
Bluetooth RF
2.4 GHz/5 GHz 802.11ac
Dual-Band Radio
1 x 1 802.11ac PHY
DOT11MAC (D11)
Chip
Common
OTP
NIC-301 AXI Backplane
AXI2AHB
AHB2AXI
ARMCR4
TCM
RAM768KB
ROM640KB
SDIOD
AXI2APB
GCI
SECI UART
and GCI-GPIOs
WLAN RAM
Sharing
WLAN 
BT Access
GCI Coex I/F
Shared LNA Control
and Other Coex I/Fs
VBAT
WL_REG_ON
BT_REG_ON
BT_HOST_WAKE
BT_DEV_WAKE
UART
PCM
I
2
S
Other GPIOs
BT
PA
32 kHz External LPO
XTAL
RF Switch Controls
SDIO 3.0
WL_HOST_WAKE
WL_DEV_WAKE
JTAG
Other GPIOs
2.4 GHz 5 GHz