Cypress EZ-USB® FX3™ SDK Quick Start Guide, Version 1.3.1 23
Note: It has been noted that changing the master clock frequency causes a
transient instability on the device interfaces, which may cause an ongoing JTAG
debug session to break. To minimize the impact of this instability, this frequency
change is performed by firmware before any of the external interfaces on the
device are initialized.
5.1.2 Setting up the IO Matrix
The next step in the device initialization is setting up the functionality for various IO
pins on the device. Almost all of the device IOs can serve multiple functions, and
the actual function to be used is selected through the
CyU3PDeviceConfigureIOMatrix API call.
Please note that some constraints apply to the possible IO configurations. For
example, it is not possible to use the SPI interface on the FX3 device if the GPIF is
running in a 32 bit wide configuration.
Any of the pins on the device can be overridden to function as a GPIO instead of
serving as part of another interface such as GPIF, UART, I2C etc. The
CyU3PDeviceConfigureIOMatrix() makes some sanity checks to ensure that a pin
that is otherwise in use, cannot be overridden as a GPIO pin.
e.g., if the UART interface is enabled using the useUart parameter; the API does
not allow any of the UART pins (TX, RX, RTS and CTS) to be used as GPIOs.
It is possible that the above checks in the API constrain the user. For example, if
the user does not plan to use flow control for the UART, there is no reason to
prevent the RTS and CTS pins from being used as GPIOs.
In such a case, the CyU3PDeviceGpioOverride() API can be used to forcibly
override the pin functionality to serve as a GPIO.
Please note that the storage ports are only available of the FX3S (CYUSB3035)
device, which does not support a 32-bit wide GPIF configuration. Therefore, the
s0Mode and s1Mode values should be set to CY_U3P_SPORT_INACTIVE for all
FX3 applications; and the isDQ32Bit value should be set to CyFalse for all FX3S
applications.
5.1.3 Using the Caches
The FX3 device implements 8 KB of instruction and data caches that can be used
to speed up instruction and data access from the ARM CPU. It is recommended
that the instruction cache be kept enabled in all applications for optimal functioning
of the firmware.
If the firmware application makes use of any CPU bound data copy actions, turning
the data cache on will improve the performance significantly.
The instruction and data caches are enabled/disabled using the
CyU3PDeviceCacheControl() API.
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