Cypress EZ-USB FX3 SDK - FX3 Programming Guidelines; Device Initialization

Cypress EZ-USB® FX3™ SDK Quick Start Guide, Version 1.3.1 22
5 FX3 Programming Guidelines
This section provides a few basic guidelines for developing applications using the
FX3 SDK.
5.1 Device Initialization
5.1.1 Clock Settings
The first step involved in initializing the FX3 device is setting up the frequencies for
various internal clocks. There are two classes of clocks on the FX3 device:
1. Some of the clocks such as the clock for the ARM CPU, the memory
mapped register access and system DMA are expected to run continuously
at all times.
2. Other clocks such as those for the USB block, the GPIF block, and the serial
peripherals are only enabled when required; i.e., when the corresponding
block init function has been called.
All of the clocks on the FX3 device are derived from a master clock which runs at
approximately 400 MHz. If the FX3 device is being clocked using a 19.2 MHz
crystal or using a 38.4 MHz clock input; the master clock frequency is set to 384
MHz by default. If the FX3 device is being clocked using a 26 MHz or 52 MHz input
clock, the master clock frequency is set to 416 MHz.
The clock frequency for the ARM CPU is set to one half of the master clock
frequency. The clock frequency for the system DMA and register access is set to
one-fourth of the master clock frequency. These frequencies can be reduced
further using the CyU3PDeviceInit() API.
If the system design requires the FX3 device to receive data on a 32 bit wide GPIF
interface running at 100 MHz (yielding a maximum data rate of 400 MBps on the
GPIF interface); a master clock setting of 384 MHz is insufficient for the system
DMA to handle the incoming data. In such a case, the master clock needs to be
changed to a value greater than 400 MHz.
This change is done through the CyU3PDeviceInit() API call. The clkCfg-
>setSysClk400 parameter passed to this function needs to be set to CyTrue to
enable this frequency change. If this parameter is set to CyTrue, the firmware
causes the master clock frequency to be changed to 403.2 MHz.