Dell PowerEdge T310 - JTAG Boundary-Scan; System Management Bus

Dell
PowerEdge T310 Technical Guide
31
8.14 System Management Bus
The Intel 3420 chipset contains a system management bus (SMBus 2.0) host interface that allows the
processor to communicate with SMBus slaves. This interface is compatible with most I
2
C devices.
Special I
2
C commands are implemented.
The chipset‘s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the chipset supports slave functionality,
including the Host Notify protocol. Hence, the host controller supports eight command protocols of
the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick
Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block
Read/Write, and Host Notify.
The chipset‘s SMBus also implements hardware-based Packet Error Checking for data robustness and
the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus devices.
8.15 JTAG Boundary-Scan
The Intel 3420 chipset adds the industry standard JTAG interface and enables Boundary-Scan in place
of the XOR chains used in previous generations of the chipset. Boundary-Scan can be used to ensure
device connectivity during the board manufacturing process. The JTAG interface allows system
manufacturers to improve efficiency by using industry available tools to test the chipset on an
assembled board. Since JTAG is a serial interface, it eliminates the need to create probe points for
every pin in an XOR chain. This eases pin breakout and trace routing and simplifies the interface
between the system and a bed-of-nails tester.