Denon AVR-5308CI - Page 80

80
AVR-5308CI / AVC-A1HD
115 P114 Z3 SSIG.DET I -
-
- Eu Z ZONE3 S-signal detect input (H : S-signal inputted)
116 P113 (DSP4 ICS) O C
-
- - Z Not used (DSP4 control pin(ADSP-21367))
117 P112 (DSP4 FLAG0) O -
Lv
- - Z Not used (DSP4 control pin(ADSP-21367))
118 P111 DAC POWER O C
-
- Ed Z DAC Power control pin
119 P110 DSP3 RST O C
-
- Ed Z DSP3(ADSP-21367)reset output pin(reset : L)
120 P107/AN7 DSP2 RST O C
-
- Ed Z DSP2(ADSP-21367)reset output pin(reset : L)
121 P106/AN6 DSP1 RST O C
-
- Ed Z DSP1(ADSP-21366)reset output pin(reset : L)
122 P105/AN5 DSP1 FLAG0/SUBnCE I -
Lv
-EdZ
DSP1 control pin(ADSP-21366)/FPGA rewrite control(MAIN FPGA&GUI FPGA
combined use)
123 P104/AN4 DSP2 FLAG0/SUBDATA_O I -
Lv
-EdZ
DSP2 control pin(ADSP-21367)/FPGA rewrite control(MAIN FPGA&GUI FPGA
combined use)
124 P103/AN3
DSP3 FLAG0
/SUBCONF_DONE
I-
Lv
-EdZ
DSP3 control pin(ADSP-21367)/FPGA rewrite control(MAIN FPGA&GUI FPGA
combined use)
125 P102/AN2 DSP2 ICS/SUBnCS O C
-
-EuZ
DSP2 control pin(ADSP-21367)/FPGA rewrite control(MAIN FPGA&GUI FPGA
combined use)
126 P101/AN1 DSP1 ICS/SUBASDI O C
-
-EuZ
DSP1 control pin(ADSP-21366)/FPGA rewrite control(MAIN FPGA&GUI FPGA
combined use)
127 AVSS AVSS - -
-
---AD GND
128 P100/AN0 DSP3 ICS/SUBDCLK O C
-
- Eu Z DSP3 control pin(ADSP-21367)/FPGA rewrite control
Pin Pin Name Symbol I/O Type
Det
Op(Int.) Op(Ext.) Res Function
Note: Pin No. : Terminal number of microcomputer.
Port Name : The name entered in the data sheet of microcomputer.
Symbol : Symbolized interface function.
I/O : Input or out of part.
“I” = Input port
“O” = Output port
Type : Composition of port in case of output port.
“C” = CMOS output
“N” = NMOS open drain output
“P” = PMOS open drain output
Op : Pull up/Pull down selection information.
“Iu” = Inner microcomputer pull up
“Id” = Inner microcomputer pull down
“Eu” = External microcomputer pull up
“Ed” = External microcomputer pull down
Det : Indicates judging state of input port. Level detection is “LV”; Edge detection is “Ed”; Detection by both shifting is “E&L”;
Serial data detection is “S” (Serial data output is also “S”).
Res : State at reset.
“H” = Outputs High Level at reset
“L” = Outputs Low Level at reset
“Z” = Becomes High impedance mode at reset
STBY : State of port when STANDBY mode.
“O/L” = Output port and “L”
“I” = Input port
Stop : State of port when Stop mode.
“O/L” = Output port and “L”
“I” = Input port