Denon AVR-550SD

8
AVR-550SD
TAS5076 (MAIN: IC100)
Pin Assignment
Block Diagram
22 23
VREGB_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
PWM_AP_4
PWM_AM_4
VALID_4
PWM_BM_4
PWM_BP_4
PWM_AP_5
PWM_AM_5
VALID_5
PWM_BM_5
PWM_BP_5
PWM_AP_6
PWM_AM_6
VALID_6
PWM_BM_6
PWM_BP_6
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
MCLK_IN
AVDD_PLL
PLL_FLT_OUT
PLL_FLT_RET
AVSS_PLL
NC
VREGA_CAP
DVSS1
NC
RESET
ERR_RCVRY
MUTE
PDN
SDA
SCL
CS0
NC
NC
25 26 27 28
79 78 77 76 7580 74 72 71 7073
29
30 31 32 33
69 68
21
67 66 65 64
34 35 36 37 38 39 40
63 62 61
NC − No internal connection
AVDD_OSC XTL_IN XTL_OUT AVSS_OSC DVSS PWM_AP1 PWM_AM_1 VALID_1 PWM_BM_1 PWM_BP_1 PWM_AP_2 PWM_AM_2 VALID_2 PWM_BM_2 PWM_BP_2 PWM_AP_3 PWM_AM_3 VALID_3 PWM_BM_3 PWM_BP_3
NC NC NC
DBSPD
CLIP
SDIN1 SDIN2 SDIN3
MCLK_OUT
SCLK
LRCLK
DVDD
DVSS
VREGC_CAP
DEM_SEL2 DEM_SEL1
M_S
DVSS1 DVSS1
NC
PWM Ch.
Output Control
AVDD_PLL AVSS_PLL VREGA_CAP VREGB_CAP VREGC_CAP DVDD_RCL DVSS_RCL DVDD_PWM DVSS_PWM
Power Supply
PLL_FLT_OUT
PLL_FLT_RET
SCLK
LRCLK
MCLKOUT
SDIN1
SDIN2
SDIN3
MCLK_IN
XTAL_OUT
XTAL_IN
DBSPD
SDA
SCL
CSO
PWM_AP_1
PWM_BP_1
PWM_AM_1
Clock,
PLL
and
Serial
Data
I/F
PDN
RESET
MUTE
CLIP
ERR_RCVY
Serial
Control
I/F
Reset,
Pwr Dwn
and
Status
Auto Mute
De-emphasis
Soft Volume
Error Recovery
Soft Mute
Clip Detect
Signal
Processing
PWM
Section
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
M_S
DM_SEL1
DM_SEL2
VALID_1
PWM_BM_1
PWM_AP_2
PWM_BP_2
PWM_AM_2
VALID_2
PWM_BM_2
PWM_AP_3
PWM_BP_3
PWM_AM_3
VALID_3
PWM_BM_3
PWM_AP_4
PWM_BP_4
PWM_AM_4
VALID_4
PWM_BM_4
PWM_AP_5
PWM_BP_5
PWM_AM_5
VALID_5
PWM_BM_5
PWM_AP_6
PWM_BP_6
PWM_AM_6
VALID_6
PWM_BM_6