Denon AVR-550SD - Connecting External Input Sources; EXT. IN Jack Usage; Speaker System Wiring; Speaker Impedance Considerations

9
AVR-550SD
TAS5182 (MAIN: IC102,103,104)
Pin assignments
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
DV
DD
DV
SS
NC
DTC_HS
DTC_LS
OC_HIGH
VRFILT
AP
AM
RESET_AB
BM
BP
CP
CM
RESET_CD
DM
DP
SHUTDOWN
ERR0
ERR1
LOW/HIZ
DV
SS
NC
NC
OC_LOW
TEMP
GV
SS
GV
DD
GLS_A
SLS_A
SHS_A
GHS_A
BST_A
DHS_A
GLS_B
SLS_B
SHS_B
GHS_B
BST_B
DHS_B
GLS_C
SLS_C
SHS_C
GHS_C
BST_C
DHS_C
GLS_D
SLS_D
SHS_D
GHS_D
BST_D
DHS_D
GV
DD
GV
SS
DP
DM
BST_D
DHS_D
GHS_D
SHS_D
GLS_D
SLS_D
CP
CM
BST_C
DHS_C
GHS_C
SHS_C
GLS_C
SLS_C
BP
BM
BST_B
DHS_B
GHS_B
SHS_B
GLS_B
SLS_B
PWM
Receiver
Timing
and
Control
HS
Gate
Drive
LS
Gate
Drive
AP
AM
BST_A
DHS_A
GHS_A
SHS_A
GLS_A
SLS_A
Protection Circuitry
Status
Bandgap
Reference
VRFILT
DTC_HS
DTC_LS
OC_HIGH
TEMP
LOW/HIZ
A – Half-Bridge Driver
PWM
Receiver
Timing
and
Control
HS
Gate
Drive
LS
Gate
Drive
PWM
Receiver
Timing
and
Control
HS
Gate
Drive
LS
Gate
Drive
PWM
Receiver
Timing
and
Control
HS
Gate
Drive
LS
Gate
Drive
B – Half-Bridge Driver
C – Half-Bridge Driver
D – Half-Bridge Driver
RESET_AB
RESET_CD
SHUTDOWN
ERR0
ERR1
DV
DD
DV
SS
GV
DD
GV
SS
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GV
DD
OC_LOW