18
18DN-S5000
1
11
12
22
23
33
34
44
TOP VIEW
Setting
Pin No. Symbol I/O Function
1 VDD2
—
VDD power supply terminal.
2 UC1 IP/O Microcomputer interface extended I/O 1. Not Used (OPEN)
3 UC2 IP/O Microcomputer interface extended I/O 2. Not Used (OPEN)
4 UC3 IP/O Microcomputer interface extended I/O 3. Not Used (OPEN)
5 UC4 IP/O Microcomputer interface extended I/O 4. Not Used (OPEN)
6 UC5 IP/O Microcomputer interface extended I/O 5. Not Used (OPEN)
7 DIT O Digital audio interface terminal.
8 NTEST IP Test terminal. Test
9 CLK I 16.9344 MHz clock input.
10 Vss
—
Ground terminal.
11 YSRDATA I Audio serial input data.
12 YLRCK I Audio serial input LR clock. Lch Rch
13 YSCK I Audio serial input bit clock.
14 ZSCK O Audio serial output bit clock.
15 ZLRCK O Audio serial output LR clock. Lch Rch
16 ZSRDATA O Audio serial output data.
17 YFLAG I RAM overflow flag for signal processing IC. Over
18 YFCLK I X’tal system frame clock.
19 YBLKCK I Sub-code block clock signal.
20 NRESET I System reset terminal. Reset
21 ZSENSE O Microcomputer interface status output.
22 VDD1
—
VDD power supply terminal.
23 YDMUTE I Forcible mute terminal. Mute
24 YMLD I Microcomputer interface latch clock.
25 YMDATA I Microcomputer interface serial data.
26 YMCLK I Microcomputer interface shift clock.
27 A10 O DRAM address 10.
28 NCAS O DRAM CAS control.
29 D2 I/O DRAM data input/output 2.
30 D3 I/O DRAM data input/output 3.
31 D0 I/O
DRAM data input/output 0.
32 D1 I/O DRAM data input/output 1.
33 NWE O DRAM WE control.
34 NRAS O DRAM RAS control.
35 A9 O DRAM address 9.
36 A8 O DRAM address 8.
37 A7 O DRAM address 7.
38 A6 O DRAM address 6.
39 A5 O DRAM address 5.
40 A4 O DRAM address 4.
41 A0 O DRAM address 0.
42 A1 O DRAM address 1.
43 A2 O DRAM address 2.
44 A3 O DRAM address 3.
LH
SM5902AF Terminal Function
SM5902AF (IC651, 652)
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