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AD83586_(U4) Pin Assignment
AD83586_(U4) Pin Diescription
Preliminary
AD83586
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Sep. 2011
Revision: 0.1 2/50
Pin Assignment
!
Pin Description
PIN NAME TYPE DESCRIPTION CHARACTERISTICS
1 SDATA1 I Serial audio data input 1 Schmitt trigger TTL input buffer
2 MS I EEPROM selection Schmitt trigger TTL input buffer
3
I PLL enable, low active Schmitt trigger TTL input buffer
4 CFG0 I 2.1 Ch/Stereo/Mono configuration pin Schmitt trigger TTL input buffer
5 CFG1 I 2.1 Ch/Stereo/Mono configuration pin Schmitt trigger TTL input buffer
6 CLK_OUT O Clock output from PLL TTL output buffer
7 DGND P Digital Ground
8 DVDD P Digital Power
9 SDATA0 I Serial audio data input 0 Schmitt trigger TTL input buffer
10 LRCIN I Left/Right clock input (Fs) Schmitt trigger TTL input buffer
11 BCLK I Bit clock input (64Fs) Schmitt trigger TTL input buffer
12 MCLK I Master clock input Schmitt trigger TTL input buffer
13 N.C.
14 VDDSA P Subwoofer channel supply A
15 SA1 O Subwoofer channel output A1
16 GNDS P Subwoofer channel ground
17 SA2 O Subwoofer channel output A2
18 VDDSA P Subwoofer channel supply A
19 VDDSB P Subwoofer channel supply B
Preliminary
AD83586
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Sep. 2011
Revision: 0.1 2/50
Pin Assignment
!
Pin Description
PIN NAME TYPE DESCRIPTION CHARACTERISTICS
1 SDATA1 I Serial audio data input 1 Schmitt trigger TTL input buffer
2 MS I EEPROM selection Schmitt trigger TTL input buffer
3
I PLL enable, low active Schmitt trigger TTL input buffer
4 CFG0 I 2.1 Ch/Stereo/Mono configuration pin Schmitt trigger TTL input buffer
5 CFG1 I 2.1 Ch/Stereo/Mono configuration pin Schmitt trigger TTL input buffer
6 CLK_OUT O Clock output from PLL TTL output buffer
7 DGND P Digital Ground
8 DVDD P Digital Power
9 SDATA0 I Serial audio data input 0 Schmitt trigger TTL input buffer
10 LRCIN I Left/Right clock input (Fs) Schmitt trigger TTL input buffer
11 BCLK I Bit clock input (64Fs) Schmitt trigger TTL input buffer
12 MCLK I Master clock input Schmitt trigger TTL input buffer
13 N.C.
14 VDDSA P Subwoofer channel supply A
15 SA1 O Subwoofer channel output A1
16 GNDS P Subwoofer channel ground
17 SA2 O Subwoofer channel output A2
18 VDDSA P Subwoofer channel supply A
19 VDDSB P Subwoofer channel supply B
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