Denon DSD300 - Page 55

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AD83586_(U4) Preliminary
 Preliminary AD83586
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc. Publication Date: Sep. 2011
Revision: 0.1 3/50
20 SB2 O Subwoofer channel output B2
21 GNDL P Subwoofer channel ground
22 SB1 O Subwoofer channel output B1
23 VDDSB P Subwoofer channel supply B
24 N.C.
25 SDA I/O I
2
C bi-directional serial data Schmitt trigger TTL input buffer
26 SCL I/O I
2
C serial clock input Schmitt trigger TTL input buffer
27 SA0 I I
2
C select address 0 Schmitt trigger TTL input buffer
28 SA1 I I
2
C select address 1 Schmitt trigger TTL input buffer
29 DEF I
Initial default volume setting
(1:Un-Mute ; 0:Mute)
Schmitt trigger TTL input buffer
30 DGND P Digital Ground
31 DVDD P Digital Power
32
PD
I Power down, low active Schmitt trigger TTL input buffer
33
ERROR
O Error status, low active Open-drain output
34
RESET
I Reset, low active Schmitt trigger TTL input buffer
35 LREX I Left/Right channel exchange Schmitt trigger TTL input buffer
36 LINEIN I
Select input data
(0:SDATA0 ; 1:SDATA1)
Schmitt trigger TTL input buffer
37 N.C.
38 VDDRA P Right channel supply A
39 RA O Right channel output A
40 GNDR P Right channel ground
41 RB O Right channel output B
42 VDDRB P Right channel supply B
43 VDDLB P Left channel supply B
44 LB O Left channel output B
45 GNDL P Left channel ground
46 LA O Left channel output A
47 VDDLA P Left channel supply A
48 N.C.