Digilent Arty Z7 - Quad SPI Flash; Quad SPI Flash Device Attributes; DDR Memory; DDR3 Memory Component

Arty Z7 Reference Manual Transfer Multisort Elektronik / tme.eu 12
It is also possible to directly configure the PL over JTAG, independent of the processor. This
can be done using the Vivado Hardware Server.
The Arty Z7 is configured to boot in Cascaded JTAG mode, which allows the PS to be
accessed via the same JTAG port as the PL. It is also possible to boot the Arty Z7 in
Independent JTAG mode by loading a jumper in JP2 and shorting it. This will cause the PS to
not be accessible from the onboard JTAG circuitry, and only the PL will be visible in the scan
chain. To access the PS over JTAG while in independent JTAG mode, users will have to route
the signals for the PJTAG peripheral over EMIO, and use an external device to communicate
with it.
4 Quad SPI Flash
The Arty Z7 features a Quad SPI serial NOR flash. The Spansion S25FL128S is used on this
board. The Multi-I/O SPI Flash memory is used to provide non-volatile code and data storage.
It can be used to initialize the PS subsystem as well as configure the PL subsystem.
The relevant device attributes are:
• 16 MB
• x1, x2, and x4 support
• Bus speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz. In Quad
SPI mode, this translates to 400Mbs
• Powered from 3.3V
The SPI Flash connects to the Zynq-7000 APSoC and supports the Quad SPI interface. This
requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined
in the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left
to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad
SPI clock frequency greater than FQSPICLK2 (See the Zynq Technical Reference manual for
more on this).
5 DDR Memory
The Arty Z7 includes an IS43TR16256A-125KBL DDR3 memory components creating a
single rank, 16-bit wide interface and a total of 512MiB of capacity. The DDR3 is connected
to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq
documentation.
The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY,
and a dedicated I/O bank. DDR3 memory interface speeds up to 533 MHz/1066 Mbps are
supported¹.