Arty Z7 Reference Manual Transfer Multisort Elektronik / tme.eu 27
Dedicated
Differential Analog
Input
See Section titled “Shield Analog I/O”
Connected to net used to drive the XADC ground
reference on the Zynq (VREFN)
XADC Analog
Voltage Reference
Connected to 1.25 V, 25mA rail used to drive the XADC
voltage reference on the Zynq (VREFP)
Digital I/O Voltage
reference
Connected to the Arty Z7 3.3V Power Rail (See the
“Power Supplies” section)
Connected to the red “SRST” button and MIO pin 12 of
the Zynq. When JP1 is shorted, it is also connected to the
DTR signal of the FTDI USB-UART bridge.
Connected to the Arty Z7 3.3V Power Rail (See the
“Power Supplies” section)
Connected to the Arty Z7 5.0V Power Rail (See the
“Power Supplies” section)
Connected to the Ground plane of Arty Z7
Connected in parallel with the external power supply
connector (J18).
Table 16.1. Shield Pin Descriptions.
16.1 Shield Digital I/O
The pins connected directly to the Zynq PL can be used as general purpose inputs or outputs.
These pins include the I2C, SPI, and general purpose I/O pins. There are 200 Ohm series
resistors between the FPGA and the digital I/O pins to help provide protection against
accidental short circuits (with the exception of the AN5-AN0 signals, which have no series
resistors, and the AN6-AN12 signals, which have 100 Ohm series resistors). The absolute
maximum and recommended operating voltages for these pins are outlined in the table below.
IO26-IO41 and A (IO42) are not accessible on the Arty Z7-10. Also, AN0-AN5 cannot be
used as Digital I/O on the Arty Z7-10. This is due to fewer number of I/O pins being available
on the Zynq-7010 than on the Zynq-7020.
Recommended
Minimum Operating
Voltage
Recommended
Maximum Operating
Voltage
Table 16.1.1. Shield Digital Voltages.
For more information on the electrical characteristics of the pins connected to the Zynq PL,
please see the Zynq-7000 datasheet from Xilinx.