Dokorder 7700 - Page 30

As
shown in Fig.8-9,
Block
Diagram
of
the CPM
Control
Block,
the
CPM control
circuit
of Model
7700
is
composed
of
(A)
a
Reference
Oscillator
Circuit
using
a
PUT
(Programmable
Unijunction
Transistor),
(B)
FG
Waveform
Shaper,
(C)
PLL
Control
Circuit,
and
(D)
Bridge-type
Motor
Drive
Circuit.
These iour
packages
are
gate
TTL
modules.
Operation
of
Circuit
Blocks
l
The PUT
Reference
Oscillator
(A)
is designed
to
oscillate
ar
512 Hz
(19
cm/s)
and
2b6 Hz
(9.5
cm/s).
This
is
in
consideration
of
the
shift-down
of the
32 kHz
quartz
oscillator for
other model.
2'
rhe FG
waveform
Shaper
(B)
shapes input
signals
into
sharp
pulses
in
order
to control
the TTL-RS
flip-flop
The
PLL
Control
circtrit
(c)
is composed
of
3 flip-flops
(frequency
comparator,
stop and
speed
acceleration).
The
Stop
and
Speed
Acceleration
flip-flops
are
controlled
by time
lagging
f
t,Tz,
or T3
so that
any
asyn_
chronous
operation
of
the circuit
will
be
pulled
into
a synchronous
mode.
The Bridged
Motor
Drive
Circuit
(D)
senses
the motor
voltage
and
current
through
a bridge
circuit,
and feeds
them
back
in
order
to
obtain
sufficient
stability
of
operation
mainly
against
power
voltage
fluctuations.
The
power
consumption
in
the
transistor
that
drives
the
DC
motor
is reduced
by
supplying
impulsive
current
to
the motor.
2
(B)
Operation
Principle
of Circuit
Blocks
in
PPL
Control
Section
1 PLL
Control
Circuit
O
Motor
design
The
torque required
of the capstan
motor
is
determined
by
the
load
applied
to the tape deck.
The
motor,s
output
torque
and
supply voltage
are
determined
so
that the motor
torque required
for
the
permitted
over- or under-voltage
condition
(110%)
may
be
obtained in each
operation mode
when
the
FG
output
f
requency
(Fv)
becomes
approximately
equal
to
the reference f
requency
(Fr).
@
Loop response
Because
of the inertial
moment
of the CPM itself
and
the load inertia
of
the
belt, flywheel
and capstan,
the
response
of
the control
loop
is
faster
during
acceleration
and slower
during
deceleration.
Since the motor
has
to be controlled for
a constant
speed,
there exist
many
quasistable
points
at
frequencies
lower
than
the reference frequency
Fr.
Thus,
a
priority
sequence logic must
establishecl
to skip
over
the
quasistable
points
and
synchronize
with
the
Fr
when changing
motor
speeds
to change
the
tape
speed.
@
PLL
btock
circuit
The
FG
output
frequency
must
change from
0 to Fr.
Due
to the loop
response
discussed
above,
the follow-
ing control
is required:
(a)
Fr )
Fv
(b)
Fr
(
Fv
(c)
Fr
)
Fv
Fr- Fv
Contro
I
block
has the
construction
as
shown below,
in
which
According
to
the control
logic
above,
the
PLL
control
Acce
leration
Deceleration
'
Fine acceleration t
I-
I
PLL
I
Synchronization
/
I
FF,
PLL
stop
flip flop
comparator
Flip flop
Fig.
8
10
Test
Stop/P
L L
Tests Acceleration/PLL
27