Eaton ELC-PB - 2.2 ELC Memory Map for ELC-PC;PA;PH controllers

ELC Programming Manual
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2-4
2.2 ELC Memory Map for ELC-PC/PA/PH controllers
Items Specifications Remarks
Control Method Stored program, cyclic scan system
I/O Processing Method
Batch processing method
(when END instruction is executed)
Fast I/O refresh instruction
can override batch update
Execution Speed
Basic instructions – 2.5μ seconds
minimum
Application instructions
varies per instruction
Program language Instructions + Ladder Logic + SFC
Program Capacity 7920 STEPS SRAM + Battery
Instructions 32 Basic instructions
178 Application
instructions
X External inputs
X0~X177, octal number
system, 128 points max.
Physical input points
Y External outputs
Y0~Y177, octal number
system, 128 points max.
Total
256 I/O
Physical output points
General M0~M511, Note 1
M512~M999, Note 3
Latched
M2000~M4095, Note 3
M
Auxiliary relay
Special
M1000~M1999
some are latched
Total
4096 bits
Main internal relay area
for general use.
T0~T199, Note 1
T192~T199 for Subroutine
100ms
T250~T255(accumulative),
6 points Note 4
T200~T239, Note 2
10ms
T240~T245(accumulative),
6 points, Note 4
T
Timer
1ms
T246~T249(accumulative),
4 points, Note 4
Total
256 bits
Contact = ON when timer
reaches preset value.
C0~C95, Note 1
16-bit count up
C96~C199, Note 3
C200~C215, Note 1
32-bit count
up/down
C216~C234, Note 3
Total
235 bits
C235~C244, 1 phase 1
input, 9 points, Note 3
C246, C247, C249, 1 phase
2 input, 3 points, Note 1
Bit Contacts
C
Counter
PC/PA
controllers,
32bit high-
speed count
up/down
C251, C252, C253, C254, 2
phase 2 input, 4 points,
Note 3
Total
16 bits
Contact = ON when
counter reaches preset
value.