Euphonix FC726 Format Converter Users Manual Introduction and Interface
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Switch #6 AES MASTER/SLAVE
When set to SLAVE (up), the Format A AES outputs lock to their corresponding
AES inputs. Within each bank, all AES outputs operate at the sample rate of the
lowest-numbered, locked AES input. For example, if the first bank (channels 1–
8) has a 44.1 kHz AES signal connected to inputs 1/2 and a 48 kHz input connect-
ed to inputs 5/6, then AES output channels 1–8 will all run at 44.1 kHz. If AES
inputs are not present on a bank, Format A will get sample clock from the Format
B Sync input. If sync is not present, Format A will then lock to the Format B Sync
Input.
When set to MASTER (down), Format A’s AES outputs get sample clock from
the Format A Sync input. If Format A sync is not present, Format A’s AES outputs
will then lock to the Format B Sync Input.
Switch #8 AES STEREO/AES MONO
Set this switch to AES Stereo (up) for the normal configuration where each AES
signal contains two discreet channels. If the sample rate is above 52 kHz (i.e., 96
or 88.2 kHz), and the AES signal connected to the FC726 implements two-wire
AES (also referred to as mono mode AES), set the switch to AES Mono (down).
This setting treats each AES signal as a single channel with a frame rate running
at half its sample rate. For example, a 96 kHz two-wire AES signal runs at 48 kHz
by using the left channel for the even samples and the right channel for the odd
samples. This switch affects both the AES inputs and outputs.
7. Format A AES Sync In
Connect an AES sync signal to this XLR connector to synchronize the Format A
MADI signal. According to the AES specification, the AES sync signal must use
the same sample rate as the incoming MADI signal to operate correctly.
NOTE: It is possible, but not recommended, to connect a MADI signal without using
a corresponding sync signal. Providing an AES or Word sync results in lower
jitter and should be used whenever possible.
8. SDIF-2 or SLAVE CLK IN
This connector can receive either an SDIF or slave clock sync signal. The FC726
automatically detects which signal type has been connected.
An SDIF device must send a word sync signal to this connector to properly con-
nect to the FC726.
9. SLAVE CLK OUT
If Slave Clk In has a valid sync signal, it is passed through to Slave Clk Out. If
Slave Clk In does not have a valid sync signal, the lowest numbered bank that is
locked and in use is selected as the clock source.
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