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Foxconn D42S - Page 34

Foxconn D42S
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27
3
Select [Disabled] to set the parameters by yourself.
The following 4 settings are valid only when the Congure DRAM Timing by SPD is set to
[Disabled].

This item controls the CAS latency. The CAS Latency is the number of clock cycles that elapse
from the time the request for data is sent to the actual memory location until the data is transmit-
ted from the module.

This item allows you to select a delay time (in clock cycles) between the CAS and RAS strobe
signals.

This item allows you to select the DRAM RAS precharge time (in clock cycles).

This item allows you to set the precharge delay time (in clock cycles).

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