D2619 (RX/TX300 S5) Technical Manual 13
3 Features
3.1 Overview
Processors
– 1 or 2 Intel
®
Xeon™ processors of the 5500 serie
– 2 processor sockets LGA1366 for Intel
®
Xeon™ processors
– integrated memory controller
– 32 KB L1 cache (on-die, data per core)
– 32 KB L1 cache (on-die, instruction per core)
– 256 KB second level cache per core
– up to 8 MB onchip shared third level cache
– 2 Intel® QuickPath Interconnect with up to 6,4 GT/s in each direction
– 2x VRM 11.1 onboard (EVRD)
Main memory
– 2x 9 slots for main memory DDR3 800 / 1066 / 1333 single-, dual- or quad-
ranked RDIMM memory modules with 2 GB, 4 GB and 8 GB
– maximum 144 GB of memory
– minimum 2 GB (1 memory module)
– maximum 32 Gbit/s band width (DDR3)
– up to 3 dual or 2 quad memory rows per channel
– ECC multiple-bit error detection and single-bit error correction
– memory scrubbing functionality
– Single Device Data Correction (SDDC) function (Chipkill™)
–Mirroring
– Sparing
Chips on the system board
– Intel
®
5520 chipset
– Intel
®
ICH10 Base (Intel
®
82801JIB)
– Intel
®
dual-port Gigabit Ethernet controller Intel 82575EB
– TPM 1.2 Infineon SLB9635 TT1.2 card
– 2 MByte SPI flash (BIOS / iSCSI, PXE Bootcode)
– Server Management controller iRMC S2 with integrated graphic controller
– 16 MByte SPI flash (code) for iRMC S2
– 1 MByte SPI flash (data) for iRMC S2
– 32Mx16-667 DDR2 SRAM for iRMC S2
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