Figure 79: Successful Autoreclose Signals logic diagram (Module 36) 165
Figure 80: Autoreclose Reset Successful Indication logic diagram (Module 37) 165
Figure 81: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39) 166
Figure 82: Autoreclose Shot Counters logic diagram (Module 41) 167
Figure 83: CB Control logic diagram (Module 43) 168
Figure 84: Circuit Breaker Trip Time Monitoring logic diagram (Module 53) 169
Figure 85: AR Lockout Logic Diagram (Module 55) 170
Figure 86: Reset Circuit Breaker Lockout Logic Diagram (Module 57) 171
Figure 87: Pole Discrepancy Logic Diagram (Module 62) 172
Figure 88: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 173
Figure 89: Check Synchronisation Monitor for CB closure (Module 60) 174
Figure 90: Voltage Monitor for CB Closure (Module 59) 175
Figure 91: Three-phase Autoreclose System Check Logic Diagram (Module 45) 177
Figure 92: CB Manual Close System Check Logic Diagram (Module 51) 178
Figure 93: Circuit Breaker Fail logic - part 1 187
Figure 94: Circuit Breaker Fail logic - part 2 188
Figure 95: Circuit Breaker Fail logic - part 3 189
Figure 96: Circuit Breaker Fail logic - part 4 190
Figure 97: CB Fail timing 192
Figure 98: Phase Overcurrent Protection logic diagram 198
Figure 99: Negative Phase Sequence Overcurrent Protection logic diagram 200
Figure 100: IDG Characteristic 203
Figure 101: Earth Fault Protection logic diagram 205
Figure 102: EPATR B characteristic shown for TMS = 1.0 208
Figure 103: Sensitive Earth Fault Protection logic diagram 208
Figure 104: Current distribution in an insulated system with C phase fault 209
Figure 105: Phasor diagrams for insulated system with C phase fault 210
Figure 106: Positioning of core balance current transformers 211
Figure 107: High Impedance REF principle 212
Figure 108: High Impedance REF Connection 213
Figure 109: Thermal overload protection logic diagram 215
Figure 110: Spreadsheet calculation for dual time constant thermal characteristic 216
Figure 111: Dual time constant thermal characteristic 216
Figure 112: Broken conductor logic 219
Figure 113: Undervoltage - single and three phase tripping mode (single stage) 225
Figure 114: Overvoltage - single and three phase tripping mode (single stage) 228
Figure 115: Residual Overvoltage logic 232
Figure 116: Residual voltage for a solidly earthed system 233
Figure 117: Residual voltage for an impedance earthed system 234
Figure 118: Underfrequency logic (single stage) 239
P54A/B/C/E Table of Figures
P54xMED-TM-EN-1 xxi